A 312-MHz CT Delta Sigma modulator using a SC feedback DAC with reduced peak current
(2007) 33rd European Solid-State Circuits Conference p.240-243- Abstract
- This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2 V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92 MHz bandwidth with a 312 MHz clock while consuming 5 mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1407524
- author
- Anderson, Martin and Sundström, Lars LU
- organization
- publishing date
- 2007
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- ESSCIRC 2007: Proceedings of the33rd EuropeanSolid State Circuits Conference
- pages
- 240 - 243
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 33rd European Solid-State Circuits Conference
- conference location
- Munich, Germany
- conference dates
- 2007-09-11 - 2007-09-13
- external identifiers
-
- wos:000252830900049
- scopus:44849115361
- ISSN
- 1930-8833
- ISBN
- 978-1-4244-1125-2
- DOI
- 10.1109/ESSCIRC.2007.4430288
- language
- English
- LU publication?
- yes
- id
- eb50ac7b-bf49-42bf-b863-78fc4f85f67b (old id 1407524)
- date added to LUP
- 2016-04-01 15:33:14
- date last changed
- 2022-01-28 05:54:34
@inproceedings{eb50ac7b-bf49-42bf-b863-78fc4f85f67b, abstract = {{This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2 V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92 MHz bandwidth with a 312 MHz clock while consuming 5 mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.}}, author = {{Anderson, Martin and Sundström, Lars}}, booktitle = {{ESSCIRC 2007: Proceedings of the33rd EuropeanSolid State Circuits Conference}}, isbn = {{978-1-4244-1125-2}}, issn = {{1930-8833}}, language = {{eng}}, pages = {{240--243}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A 312-MHz CT Delta Sigma modulator using a SC feedback DAC with reduced peak current}}, url = {{http://dx.doi.org/10.1109/ESSCIRC.2007.4430288}}, doi = {{10.1109/ESSCIRC.2007.4430288}}, year = {{2007}}, }