Design of low-power, 1GS/s throughput FFT processor for MIMO-OFDM UWB communication system
(2007) 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 p.2594-2597- Abstract
- A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which is based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently for MIMO applications. The 8PFB structure efficiently brings the throughput of the processor up to 1GS/s and the chances of register reverse down, reducing the power dissipation remarkably. Meanwhile the modified shift-add algorithm can remove complex multipliers in the FFT processor.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1686543
- author
- Liu, Liang LU ; Wang, Xuejing ; Ye, Fan and Ren, Junyan
- publishing date
- 2007
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- [Host publication title missing]
- pages
- 2594 - 2597
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
- conference location
- New Orleans, LA, United States
- conference dates
- 2007-05-27 - 2007-05-30
- external identifiers
-
- scopus:34548836347
- ISBN
- 1-4244-0920-9
- DOI
- 10.1109/ISCAS.2007.377846
- language
- English
- LU publication?
- no
- id
- 94c59727-ae2f-4e8a-8a9c-dc23c84273f8 (old id 1686543)
- date added to LUP
- 2016-04-04 11:11:42
- date last changed
- 2024-01-12 23:38:43
@inproceedings{94c59727-ae2f-4e8a-8a9c-dc23c84273f8, abstract = {{A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which is based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently for MIMO applications. The 8PFB structure efficiently brings the throughput of the processor up to 1GS/s and the chances of register reverse down, reducing the power dissipation remarkably. Meanwhile the modified shift-add algorithm can remove complex multipliers in the FFT processor.}}, author = {{Liu, Liang and Wang, Xuejing and Ye, Fan and Ren, Junyan}}, booktitle = {{[Host publication title missing]}}, isbn = {{1-4244-0920-9}}, language = {{eng}}, pages = {{2594--2597}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Design of low-power, 1GS/s throughput FFT processor for MIMO-OFDM UWB communication system}}, url = {{http://dx.doi.org/10.1109/ISCAS.2007.377846}}, doi = {{10.1109/ISCAS.2007.377846}}, year = {{2007}}, }