Energy-Efficient Redundant Execution for Chip Multiprocessors
Subramanyan, Pramod ; Singh, Virendra ; Saluja, Kewal K. and Larsson, Erik LU
(2010)
Great Lakes Symposium on VLSI (GLSVLSI'10), 2010
p.143-146
- Abstract
- Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2340845
- author
- Subramanyan, Pramod
; Singh, Virendra
; Saluja, Kewal K.
and Larsson, Erik
LU
- publishing date
- 2010
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- Proceedings of the 20th symposium on Great lakes symposium on VLSI
- pages
- 143 - 146
- conference name
- Great Lakes Symposium on VLSI (GLSVLSI'10), 2010
- conference location
- Providence, United States
- conference dates
- 2010-05-16 - 2010-05-18
- external identifiers
-
- scopus:77954513706
- ISBN
- 978-1-4503-0012-4
- DOI
- 10.1145/1785481.1785516
- language
- English
- LU publication?
- no
- id
- 060ecb2c-c345-47fd-80b4-4b5cad9fc7ef (old id 2340845)
- date added to LUP
- 2016-04-04 14:13:10
- date last changed
- 2022-01-30 02:39:00
@inproceedings{060ecb2c-c345-47fd-80b4-4b5cad9fc7ef,
abstract = {{Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.}},
author = {{Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K. and Larsson, Erik}},
booktitle = {{Proceedings of the 20th symposium on Great lakes symposium on VLSI}},
isbn = {{978-1-4503-0012-4}},
language = {{eng}},
pages = {{143--146}},
title = {{Energy-Efficient Redundant Execution for Chip Multiprocessors}},
url = {{http://dx.doi.org/10.1145/1785481.1785516}},
doi = {{10.1145/1785481.1785516}},
year = {{2010}},
}