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Power Efficient Redundant Execution for Chip Multiprocessors

Subramanyan, Pramod ; Singh, Virendra ; Saluja, Kewal K. and Larsson, Erik LU orcid (2009) Workshop on Dependable and Secure Nanocomputing p.1-6
Abstract
This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1.2%.
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author
; ; and
publishing date
type
Contribution to conference
publication status
published
subject
pages
1 - 6
conference name
Workshop on Dependable and Secure Nanocomputing
conference location
Lisbon, Portugal
conference dates
2009-06-29
language
English
LU publication?
no
id
9df03b54-9b01-40cf-af04-d6cd07482090 (old id 2340910)
date added to LUP
2016-04-04 13:09:01
date last changed
2018-11-21 21:12:26
@misc{9df03b54-9b01-40cf-af04-d6cd07482090,
  abstract     = {{This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1.2%.}},
  author       = {{Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K. and Larsson, Erik}},
  language     = {{eng}},
  pages        = {{1--6}},
  title        = {{Power Efficient Redundant Execution for Chip Multiprocessors}},
  year         = {{2009}},
}