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A digitally controlled PLL for SoC applications

Olsson, Thomas LU and Nilsson, Peter LU (2004) In IEEE Journal of Solid-State Circuits 39(5). p.751-760
Abstract
A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-mum standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm(2). In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally... (More)
A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-mum standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm(2). In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested. (Less)
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author
and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
phase-locked loop (PLL), oscillator, VHDL, time-to-digital
in
IEEE Journal of Solid-State Circuits
volume
39
issue
5
pages
751 - 760
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000221116800004
  • scopus:2442446545
ISSN
0018-9200
DOI
10.1109/JSSC.2004.826333
language
English
LU publication?
yes
id
819d5c34-c001-4192-b0a8-5864df9b0b64 (old id 280443)
date added to LUP
2016-04-01 15:58:20
date last changed
2022-04-22 18:43:13
@article{819d5c34-c001-4192-b0a8-5864df9b0b64,
  abstract     = {{A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-mum standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm(2). In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested.}},
  author       = {{Olsson, Thomas and Nilsson, Peter}},
  issn         = {{0018-9200}},
  keywords     = {{phase-locked loop (PLL); oscillator; VHDL; time-to-digital}},
  language     = {{eng}},
  number       = {{5}},
  pages        = {{751--760}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Journal of Solid-State Circuits}},
  title        = {{A digitally controlled PLL for SoC applications}},
  url          = {{http://dx.doi.org/10.1109/JSSC.2004.826333}},
  doi          = {{10.1109/JSSC.2004.826333}},
  volume       = {{39}},
  year         = {{2004}},
}