Sizing of Dual-V-T Gates for Sub-V-T Circuits
(2012) IEEE Subthreshold Microelectronics Conference (SubVT)- Abstract
- This paper presents a novel method to improve the performance of sub-threshold (sub-V-T) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3930503
- author
- Mohammadi, Babak LU ; Sherazi, Syed Muhammad Yasser LU and Rodrigues, Joachim LU
- organization
- publishing date
- 2012
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2012 IEEE Subthreshold Microelectronics Conference (SubVT)
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE Subthreshold Microelectronics Conference (SubVT)
- conference dates
- 2012-10-09 - 2012-10-10
- external identifiers
-
- wos:000319473400008
- scopus:84873539535
- ISBN
- 978-1-4673-1586-9
- DOI
- 10.1109/SubVT.2012.6404305
- language
- English
- LU publication?
- yes
- id
- 022a53f3-8898-4817-8e8e-ed3a1133612d (old id 3930503)
- date added to LUP
- 2016-04-04 10:50:32
- date last changed
- 2022-01-29 20:53:14
@inproceedings{022a53f3-8898-4817-8e8e-ed3a1133612d, abstract = {{This paper presents a novel method to improve the performance of sub-threshold (sub-V-T) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.}}, author = {{Mohammadi, Babak and Sherazi, Syed Muhammad Yasser and Rodrigues, Joachim}}, booktitle = {{2012 IEEE Subthreshold Microelectronics Conference (SubVT)}}, isbn = {{978-1-4673-1586-9}}, language = {{eng}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Sizing of Dual-V-T Gates for Sub-V-T Circuits}}, url = {{http://dx.doi.org/10.1109/SubVT.2012.6404305}}, doi = {{10.1109/SubVT.2012.6404305}}, year = {{2012}}, }