Power Savings in Digital Filters for Wireless Communication
(2013) European Conference on Circuit Theory and Design (ECCTD 2013)- Abstract
- This paper presents a methodology to reduce the power consumption, silicon area, as well as increasing the performance, in digital filters that are feasible for wireless communication circuitries. The method is based on arithmetic reductions in a wave digital filter. Basically, the multipliers are removed to reduce the number of arithmetic operations. All parameters including the dynamic and static power consumption, the silicon area, as well as the delay time are reduced substantially, without any need for trade-offs. The overall improvements in area, power consumption, and delay time, are around 50%, at an average.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4023865
- author
- Nilsson, Peter LU ; Gundarapu, Anusha and Sherazi, Syed Muhammad Yasser LU
- organization
- publishing date
- 2013
- type
- Contribution to conference
- publication status
- published
- subject
- keywords
- Static Power, Dynamic Power, Digital Filters, Half-band Filters, Low Leakage, Integrated Circuit, IC, ASIC, CMOS.
- conference name
- European Conference on Circuit Theory and Design (ECCTD 2013)
- conference location
- Dresden, Germany
- conference dates
- 2013-09-08 - 2013-09-12
- external identifiers
-
- scopus:84892649318
- language
- English
- LU publication?
- yes
- id
- b1aa9a43-edad-49a7-bed8-73afb702da00 (old id 4023865)
- date added to LUP
- 2016-04-04 13:57:56
- date last changed
- 2022-01-30 01:12:42
@misc{b1aa9a43-edad-49a7-bed8-73afb702da00, abstract = {{This paper presents a methodology to reduce the power consumption, silicon area, as well as increasing the performance, in digital filters that are feasible for wireless communication circuitries. The method is based on arithmetic reductions in a wave digital filter. Basically, the multipliers are removed to reduce the number of arithmetic operations. All parameters including the dynamic and static power consumption, the silicon area, as well as the delay time are reduced substantially, without any need for trade-offs. The overall improvements in area, power consumption, and delay time, are around 50%, at an average.}}, author = {{Nilsson, Peter and Gundarapu, Anusha and Sherazi, Syed Muhammad Yasser}}, keywords = {{Static Power; Dynamic Power; Digital Filters; Half-band Filters; Low Leakage; Integrated Circuit; IC; ASIC; CMOS.}}, language = {{eng}}, title = {{Power Savings in Digital Filters for Wireless Communication}}, year = {{2013}}, }