ASIC Implementation of a Delayless Acoustic Echo Canceller: Architecture and Arithmetic

Abstract

Application specific digital signal processors are superior compared to standard digital signal processors in a number of application fields, mainly due to high throughput and low power consumption traded for flexibility. This thesis deals with two areas related to hardware implementation of custom digital signal processors: design methodology and efficient implementation of arithmetic circuits. A delayless acoustic echo canceller is chosen as an example algorithm for custom hardware implementation. The canceller algorithm with no signal path delay is suitable in telecommunication applications, and has a high implementation complexity both in number of operations per second and in the variety of signal processing elements it is composed of. The design methodology developed and applied during the echo canceller hardware implementation is presented together with a number of optimizations applicable to the algorithm, architecture, and arithmetic design levels. The work on digital arithmetic circuits includes efficient implementation of dividers and complex multipliers. A configurable divider architecture for use in a wide range of applications is proposed. The divider is based on digit recurrence algorithms. A parameterized complex multiplier designed for low power consumption and high throughput applications is presented. The multiplier is based on distributed arithmetic, offset binary coding, and adder trees. Furthermore, an arithmetic co-optimization between two algorithms, the fast Fourier transform and the FIR filter, is proposed. The acoustic echo canceller chip has been fabricated and verified for functionality, throughput, and power consumption.

• author: Berkeman, Anders
• supervisor: [unknown] [unknown]
• opponent: Prof Wanhammar, Lars
• organization: Department of Electrical and Information Technology
• publishing date: 2002
• type: Thesis
• publication status: published
• subject: Electrical Engineering, Electronic Engineering, Information Engineering
• keywords: Signal processing, Signalbehandling, Digital Arithmetic, Acoustic Echo Cancellation, Hardware Implementation, Digital ASIC Design, Digital Signal Processing
• pages: 191 pages
• defense location: E:1406
• defense date: 2002-12-06 10:15:00
• ISBN: 91-628-5463-1
• language: English
• LU publication?: yes
• additional info: Article: A. Berkeman, V. Öwall, and M. Torkelson,"A Low Logic Depth Complex Multiplier using Distributed Arithmetic,"IEEE Journal of Solid-State Circuits,pp. 656-659, Vol. 35, Nr. 4, April 2000.A. Berkeman, V. Öwall, and M. Torkelson,"Co-Optimization of FFT and FIR in a Delayless Acoustic Echo Canceller Implementation,"in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS2000),May 28-31, 2000, Geneva, SwitzerlandA. Berkeman, V. Öwall, and M. Torkelson,"A Prestudy of an Echo Canceler Implementation,"in Proceedings of the International Conference on Signal Processing Applications and Technology (ICSPAT'99),November 1-4, 1999, Orlando, Florida, USAA. Berkeman and V. Öwall,"A Configurable Divider using Digit Recurrence,"submitted to IEEE International Symposium on Circuits and Systems, 2003.A. Berkeman and V. Öwall,"Efficient Implementation of an FFT-FIR Structure Using a Distributed Arithmetic Multiplier,"Submitted to IEEE Transactions on Very Large Scale Integration (VLSI) SystemsA. Berkeman and V. "Owall,"Custom Silicon Implementation of a Delayless Acoustic Echo Canceller Algorithm,"in preparation.
• id: 3ea5836b-e441-4e87-ac6e-7845832f3f1c (old id 465276)
• date added to LUP: 2016-04-01 16:05:26
• date last changed: 2018-11-21 20:38:37