A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL
(2015) IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015 p.95-98- Abstract
- A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/5101356
- author
- Wu, Ying ; Lu, Ping LU and Staszewski, Robert Bogdan
- organization
- publishing date
- 2015
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
- pages
- 95 - 98
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015
- conference location
- Phoenix, Arizona, United States
- conference dates
- 2015-05-17 - 2015-05-19
- external identifiers
-
- scopus:84975735384
- ISBN
- 978-1-4799-7642-3
- DOI
- 10.1109/RFIC.2015.7337713
- language
- English
- LU publication?
- yes
- id
- 1555f350-6496-471f-98f9-ebab25f1bc9f (old id 5101356)
- date added to LUP
- 2016-04-04 12:14:50
- date last changed
- 2022-04-24 01:55:36
@inproceedings{1555f350-6496-471f-98f9-ebab25f1bc9f, abstract = {{A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.}}, author = {{Wu, Ying and Lu, Ping and Staszewski, Robert Bogdan}}, booktitle = {{2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)}}, isbn = {{978-1-4799-7642-3}}, language = {{eng}}, pages = {{95--98}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL}}, url = {{http://dx.doi.org/10.1109/RFIC.2015.7337713}}, doi = {{10.1109/RFIC.2015.7337713}}, year = {{2015}}, }