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A low-complexity method for distributed clocking on digital ASICs

Olsson, Thomas LU and Nilsson, Peter LU (2004) Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits p.344-347
Abstract
A low-complexity method using synchronous wrappers is proposed to simplify communication between modules using unsynchronized clocks. To test the method, it is implemented together with a divider and an FFT co-processor. The divider with synchronous wrapper and local clock generator, delivering a 500 MHz clock, is synthesized and verified using post-synthesis simulations for a 0.18 μm 1.8 V CMOS technology. A complete description of the wrapper in synthesizable VHDL-code including local a local clock generator makes the method portable between technologies
Please use this url to cite or link to this publication:
author
and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
local clock generator, divider, FFT coprocessor, unsynchronized clocks, digital ASIC, synchronous wrappers, distributed clocking, low-complexity method, CMOS technology, post-synthesis simulation, VHDL-code, large SoC, 1.8 V
host publication
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (IEEE Cat. No.04EX909)
pages
344 - 347
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
conference location
Fukuoka, Japan
conference dates
2004-08-04 - 2004-08-05
external identifiers
  • wos:000224435400072
  • scopus:14544277111
ISBN
0-7803-8637-X
DOI
10.1109/APASIC.2004.1349492
language
English
LU publication?
yes
id
3b38104b-43d3-4fb4-8537-a9695da7ed1f (old id 614749)
date added to LUP
2016-04-04 11:17:32
date last changed
2022-01-29 21:36:28
@inproceedings{3b38104b-43d3-4fb4-8537-a9695da7ed1f,
  abstract     = {{A low-complexity method using synchronous wrappers is proposed to simplify communication between modules using unsynchronized clocks. To test the method, it is implemented together with a divider and an FFT co-processor. The divider with synchronous wrapper and local clock generator, delivering a 500 MHz clock, is synthesized and verified using post-synthesis simulations for a 0.18 μm 1.8 V CMOS technology. A complete description of the wrapper in synthesizable VHDL-code including local a local clock generator makes the method portable between technologies}},
  author       = {{Olsson, Thomas and Nilsson, Peter}},
  booktitle    = {{Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (IEEE Cat. No.04EX909)}},
  isbn         = {{0-7803-8637-X}},
  keywords     = {{local clock generator; divider; FFT coprocessor; unsynchronized clocks; digital ASIC; synchronous wrappers; distributed clocking; low-complexity method; CMOS technology; post-synthesis simulation; VHDL-code; large SoC; 1.8 V}},
  language     = {{eng}},
  pages        = {{344--347}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A low-complexity method for distributed clocking on digital ASICs}},
  url          = {{http://dx.doi.org/10.1109/APASIC.2004.1349492}},
  doi          = {{10.1109/APASIC.2004.1349492}},
  year         = {{2004}},
}