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Design of coarse-grained dynamically reconfigurable architecture for DSP applications

Zhang, Chenxin LU ; Lenart, Thomas ; Svensson, Henrik and Öwall, Viktor LU (2009) 2009 International Conference on ReConFigurable Computing and FPGAs p.338-343
Abstract
This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32... (More)
This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution. (Less)
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Coarse-grained reconfigurable architecture, FFT., Dynamically reconfigurable cell array, Hybrid interconnect
host publication
International Conference on Reconfigurable Computing and FPGAs
pages
6 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2009 International Conference on ReConFigurable Computing and FPGAs
conference location
Cancun, Mexico
conference dates
2009-12-09 - 2009-12-11
external identifiers
  • wos:000285022700058
  • scopus:77950473150
ISBN
978-0-7695-3917-1
DOI
10.1109/ReConFig.2009.49
language
English
LU publication?
yes
id
89e4fd19-b760-4e36-86c0-79f33c4606ee (old id 1492898)
alternative location
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5382079&matchBoolean%3Dtrue%26searchField%3DSearch_All%26queryText%3D(Design+of+coarse-grained+dynamically+reconfigurable+architecture+for+DSP+applications)
date added to LUP
2016-04-04 11:12:22
date last changed
2022-01-29 21:31:01
@inproceedings{89e4fd19-b760-4e36-86c0-79f33c4606ee,
  abstract     = {{This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.}},
  author       = {{Zhang, Chenxin and Lenart, Thomas and Svensson, Henrik and Öwall, Viktor}},
  booktitle    = {{International Conference on Reconfigurable Computing and FPGAs}},
  isbn         = {{978-0-7695-3917-1}},
  keywords     = {{Coarse-grained reconfigurable architecture; FFT.; Dynamically reconfigurable cell array; Hybrid interconnect}},
  language     = {{eng}},
  pages        = {{338--343}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Design of coarse-grained dynamically reconfigurable architecture for DSP applications}},
  url          = {{http://dx.doi.org/10.1109/ReConFig.2009.49}},
  doi          = {{10.1109/ReConFig.2009.49}},
  year         = {{2009}},
}