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- 2018
- Building and operating a real-time massive MIMO testbed - Lessons learned
- A 1.8Gb/s 70.6pJ/b 128x16 Link-Adaptive Near-Optimal Massive MIMO Detector in 28nm UTBB-FDSOI
- An Area-Efficient On-Chip Memory System for Massive MIMO Using Channel Data Compression
- A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI
- 2017
- A low latency and area efficient FFT processor for massive MIMO systems
- Architecture Design of a Memory Subsystem for Massive MIMO Baseband Processing
- The World's First Real-Time Testbed for Massive MIMO: Design, Implementation, and Validation
- Reducing On-chip Memory for Massive MIMO Baseband Processing using Channel Compression
- Implementation of Low-latency Signal Processing and Data Shuffling for TDD massive MIMO Systems
- 2015
- Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing: From Algorithm to Architecture