Integrated Electronic Systems
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- 2026
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Mark
Spur Analysis and Linearity Enhancement in Fractional-N Phase Locked Loops Through Parallel Sigma–Delta Modulators With Time Offsets
- Contribution to journal › Article
-
Mark
Attacks exploiting on-chip Instruments and IJTAG protection
(2026)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Embedded tutorial : security in reconfigurable scan networks
(2026)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Securing reconfigurable scan networks
(2026) LSI Test Workshop
- Contribution to conference › Paper, not in proceeding
-
Mark
On the importance of time constants in spiking neural networks
(2026) p.193-198
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Multi-user XR offloading via massive MIMO : a system-level analysis using a real-life dataset
(2026)
- Working paper/Preprint › Preprint in preprint archive
-
Mark
Threats and protection of on-chip test features throughout the lifetime of Integrated Circuits
(2026) In Series of licentiate and doctoral theses
- Thesis › Licentiate thesis
- 2025
-
Mark
Large Language Models for Printed Circuit Board Test Generation
(2025) 26th IEEE Latin-American Test Symposium (LATS2025)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Securing reconfigurable scan networks against data sniffing and data alteration attacks
(2025) 30th IEEE European Test Symposium
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Secure and efficient sharing of on-chip resources
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
