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Designing pipeline FFT processor for OFDM (de)modulation

He, Shousheng LU and Torkelson, Mats LU (1998) 1998 URSI International Symposium on Signals, Systems, and Electronics, ISSSE 98. In [Host publication title missing] p.257-262
Abstract
The FFT processor is one of the key components in the implementation of wideband OFDM systems. Architectures with a structured pipeline have been used to meet the fast, real-time processing demand and low-power consumption requirement in a mobile environment. Architectures based on new forms of FFT, the radix-2i algorithm derived by cascade decomposition, is proposed. By exploiting the spatial regularity of the new algorithm, the requirement for both dominant elements in VLSI implementation, the memory size and the number of complex multipliers, have been minimized. Progressive wordlength adjustment has been introduced to optimize the total memory size with a given signal-to-quantization-noise-ratio (SQNR) requirement in fixed-point... (More)
The FFT processor is one of the key components in the implementation of wideband OFDM systems. Architectures with a structured pipeline have been used to meet the fast, real-time processing demand and low-power consumption requirement in a mobile environment. Architectures based on new forms of FFT, the radix-2i algorithm derived by cascade decomposition, is proposed. By exploiting the spatial regularity of the new algorithm, the requirement for both dominant elements in VLSI implementation, the memory size and the number of complex multipliers, have been minimized. Progressive wordlength adjustment has been introduced to optimize the total memory size with a given signal-to-quantization-noise-ratio (SQNR) requirement in fixed-point processing. A new complex multiplier based on distributed arithmetic further enhanced the area/power efficiency of the design. A single-chip processor for 1 K complex point FFT transform is used to demonstrate the design issues under consideration. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
fast Fourier transforms, distributed arithmetic, digital signal processing chips, demodulation, OFDM modulation, VLSI, multiplying circuits, pipeline processing
in
[Host publication title missing]
pages
257 - 262
conference name
1998 URSI International Symposium on Signals, Systems, and Electronics, ISSSE 98.
external identifiers
  • Scopus:0032217939
ISBN
0-7803-4900-8
DOI
10.1109/ISSSE.1998.738077
language
English
LU publication?
yes
id
734ac4f6-1bfb-47b6-a054-ac9d2d9f1570 (old id 1785628)
date added to LUP
2011-02-10 10:05:20
date last changed
2016-04-16 11:23:28
@misc{734ac4f6-1bfb-47b6-a054-ac9d2d9f1570,
  abstract     = {The FFT processor is one of the key components in the implementation of wideband OFDM systems. Architectures with a structured pipeline have been used to meet the fast, real-time processing demand and low-power consumption requirement in a mobile environment. Architectures based on new forms of FFT, the radix-2i algorithm derived by cascade decomposition, is proposed. By exploiting the spatial regularity of the new algorithm, the requirement for both dominant elements in VLSI implementation, the memory size and the number of complex multipliers, have been minimized. Progressive wordlength adjustment has been introduced to optimize the total memory size with a given signal-to-quantization-noise-ratio (SQNR) requirement in fixed-point processing. A new complex multiplier based on distributed arithmetic further enhanced the area/power efficiency of the design. A single-chip processor for 1 K complex point FFT transform is used to demonstrate the design issues under consideration.},
  author       = {He, Shousheng and Torkelson, Mats},
  isbn         = {0-7803-4900-8},
  keyword      = {fast Fourier transforms,distributed arithmetic,digital signal processing chips,demodulation,OFDM modulation,VLSI,multiplying circuits,pipeline processing},
  language     = {eng},
  pages        = {257--262},
  series       = {[Host publication title missing]},
  title        = {Designing pipeline FFT processor for OFDM (de)modulation},
  url          = {http://dx.doi.org/10.1109/ISSSE.1998.738077},
  year         = {1998},
}