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Design and implementation of a 1024-point pipeline FFT processor

He, Shousheng LU and Torkelson, Mats LU (1998) The IEEE Custom Integrated Circuits Conference, 1998 In [Host publication title missing] p.131-134
Abstract
The design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radix-22 algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in 0.5 μm CMOS technology and takes an area of 40 mm2. With 3.3 V power supply, it can compute 2n , n=0, 1, ..., 10 complex point forward and inverse FFT in real time with up to 30 MHz sampling frequency. The SQNR is above 50 dB for white noise input.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
CMOS digital integrated circuits, VLSI, digital signal processing chips, fast Fourier transforms, pipeline processing
in
[Host publication title missing]
pages
131 - 134
conference name
The IEEE Custom Integrated Circuits Conference, 1998
external identifiers
  • Scopus:0031633013
ISBN
0-7803-4292-5
DOI
10.1109/CICC.1998.694922
language
English
LU publication?
yes
id
a1c9dd7e-c3bd-4875-aeac-4369d3df4ac9 (old id 1785647)
date added to LUP
2011-02-10 10:06:11
date last changed
2016-04-16 11:32:28
@misc{a1c9dd7e-c3bd-4875-aeac-4369d3df4ac9,
  abstract     = {The design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radix-22 algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in 0.5 μm CMOS technology and takes an area of 40 mm2. With 3.3 V power supply, it can compute 2n , n=0, 1, ..., 10 complex point forward and inverse FFT in real time with up to 30 MHz sampling frequency. The SQNR is above 50 dB for white noise input.},
  author       = {He, Shousheng and Torkelson, Mats},
  isbn         = {0-7803-4292-5},
  keyword      = {CMOS digital integrated circuits,VLSI,digital signal processing chips,fast Fourier transforms,pipeline processing},
  language     = {eng},
  pages        = {131--134},
  series       = {[Host publication title missing]},
  title        = {Design and implementation of a 1024-point pipeline FFT processor},
  url          = {http://dx.doi.org/10.1109/CICC.1998.694922},
  year         = {1998},
}