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Power Constrained Test Scheduling for 3D Stacked Chips: poster

Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU (2010) 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
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author
organization
publishing date
type
Contribution to conference
publication status
published
subject
conference name
1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
language
English
LU publication?
no
id
844b79c2-f01f-455f-8acc-53b3e9ee2a47 (old id 2340810)
date added to LUP
2012-02-10 14:02:10
date last changed
2016-04-16 11:09:42
@misc{844b79c2-f01f-455f-8acc-53b3e9ee2a47,
  author       = {Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik},
  language     = {eng},
  title        = {Power Constrained Test Scheduling for 3D Stacked Chips: poster},
  year         = {2010},
}