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A Technique for Optimization of System-on-Chip Test Data Transportation

Larsson, Anders; Larsson, Erik LU ; Eles, Petru Ion and Peng, Zebo (2004) 9th IEEE European Test Symposium p.179-180
Abstract
We propose a Tabu-search-based technique for time-constrained SOC (System-on-Chip) test data transportation. The technique makes use of the existing bus structure, where the advantage is, compared to adding dedicated test buses, that no additional routing is needed. In order to speed up the testing and to fulfill the time constraint, we introduce a buffer at each core, which in combination with dividing tests into smaller packages allows concurrent application of tests on a sequential bus. Our technique minimizes the combined cost of the added buffers and the test control logic. We have implemented the technique, and experimental results indicate that it produces high quality results at low computational cost.
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to conference
publication status
published
subject
keywords
system-on-chip, data transportation, test control logic
pages
179 - 180
conference name
9th IEEE European Test Symposium
language
English
LU publication?
no
id
c5b48721-4854-46e4-88e9-a7c5c95b59dd (old id 2341156)
alternative location
http://www.ida.liu.se/labs/eslab/publications/pap/db/ets04.pdf
date added to LUP
2012-02-10 13:27:23
date last changed
2016-06-29 09:01:26
@misc{c5b48721-4854-46e4-88e9-a7c5c95b59dd,
  abstract     = {We propose a Tabu-search-based technique for time-constrained SOC (System-on-Chip) test data transportation. The technique makes use of the existing bus structure, where the advantage is, compared to adding dedicated test buses, that no additional routing is needed. In order to speed up the testing and to fulfill the time constraint, we introduce a buffer at each core, which in combination with dividing tests into smaller packages allows concurrent application of tests on a sequential bus. Our technique minimizes the combined cost of the added buffers and the test control logic. We have implemented the technique, and experimental results indicate that it produces high quality results at low computational cost.},
  author       = {Larsson, Anders and Larsson, Erik and Eles, Petru Ion and Peng, Zebo},
  keyword      = {system-on-chip,data transportation,test control logic},
  language     = {eng},
  pages        = {179--180},
  title        = {A Technique for Optimization of System-on-Chip Test Data Transportation},
  year         = {2004},
}