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A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS

Abdulaziz, Mohammed LU ; Shakir, Muhammed; Lu, Ping LU and Andreani, Pietro LU (2011) 29th Norchip conference, 2011 In [Host publication title missing]
Abstract
A divider-less all digital phase locked loop (ADPLL) with a high frequency resolution is implemented. All blocks excluding digitally controlled oscillator (DCO) and time to digital converter (TDC) are realized in standard digital design which consumes less power. The DCO core adopts an improved source-varactor LC resonant tank to achieve a 20KHz frequency resolution. With the help of an additional ΔΣ modulator, the final frequency resolution is 625Hz. This work is simulated in 90nm CMOS process technology and consumes 7.6mW (DCO occupies 97.4%) under the power supply of 1.2V.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
voltage 1.2 V, time to digital converter, standard digital design, source-varactor LC resonant tank, size 90 nm, power 7.6 mW, high frequency resolution, frequency 625 GHz, frequency 20 kHz, frequency 2.7 GHz, divider-less all digital phase-locked loop, digitally controlled oscillator, delta sigma modulator, CMOS process technology
in
[Host publication title missing]
pages
4 pages
conference name
29th Norchip conference, 2011
external identifiers
  • Scopus:84856846477
ISBN
978-1-4577-0514-4
DOI
10.1109/NORCHP.2011.6126743
language
English
LU publication?
yes
id
17fdb4d7-a1ba-4c28-8a79-4a1b14f60e21 (old id 2429907)
date added to LUP
2012-03-29 10:37:44
date last changed
2016-10-13 05:01:49
@misc{17fdb4d7-a1ba-4c28-8a79-4a1b14f60e21,
  abstract     = {A divider-less all digital phase locked loop (ADPLL) with a high frequency resolution is implemented. All blocks excluding digitally controlled oscillator (DCO) and time to digital converter (TDC) are realized in standard digital design which consumes less power. The DCO core adopts an improved source-varactor LC resonant tank to achieve a 20KHz frequency resolution. With the help of an additional ΔΣ modulator, the final frequency resolution is 625Hz. This work is simulated in 90nm CMOS process technology and consumes 7.6mW (DCO occupies 97.4%) under the power supply of 1.2V.},
  author       = {Abdulaziz, Mohammed and Shakir, Muhammed and Lu, Ping and Andreani, Pietro},
  isbn         = {978-1-4577-0514-4},
  keyword      = {voltage 1.2 V,time to digital converter,standard digital design,source-varactor LC resonant tank,size 90 nm,power 7.6 mW,high frequency resolution,frequency 625 GHz,frequency 20 kHz,frequency 2.7 GHz,divider-less all digital phase-locked loop,digitally controlled oscillator,delta sigma modulator,CMOS process technology},
  language     = {eng},
  pages        = {4},
  series       = {[Host publication title missing]},
  title        = {A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS},
  url          = {http://dx.doi.org/10.1109/NORCHP.2011.6126743},
  year         = {2011},
}