1 – 5 of 5
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=""
width=""
height=""
allowtransparency="true"
frameborder="0">
</iframe>
- 2013
-
Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
- Contribution to journal › Article
-
Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
(2012) GigaHertz Symposium 2012
- Contribution to conference › Abstract
- 2011
-
Mark
A mixed mode design flow for multi GHz ADPLLs
(2011) 29th Norchip conference, 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
(2011) 29th Norchip conference, 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding