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A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency

Lu, Ping LU ; Andreani, Pietro LU and Liscidini, Antonio (2013) IEEE RFIC p.151-154
Abstract
The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X-axis phases and Y-axis phases (based on 2-D definition) can be used, rather than only the diagonal line. The large latency time inherited from Vernier structure is therefore dramatically reduced. The TDC is implemented in a 90nm CMOS process and consumes 1.8mA from 1.2V. The measured input range can safely cover a full period of a 50MHz sampling signal. With the same delay elements, the latency time is less than 1/6 of that needed in a standard Vernier TDC.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
GRO, Vernier, Time to digital converter, 2-D
host publication
IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013
pages
151 - 154
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE RFIC
conference location
Seattle, Washington, United States
conference dates
2013-06-02
external identifiers
  • scopus:84883358515
ISSN
1529-2517
ISBN
978-1-4673-6059-3
DOI
10.1109/RFIC.2013.6569547
language
English
LU publication?
yes
id
88780e8f-ca05-4e81-87cb-819c2f9e04c2 (old id 3558806)
date added to LUP
2013-02-28 13:23:23
date last changed
2019-06-19 02:28:44
@inproceedings{88780e8f-ca05-4e81-87cb-819c2f9e04c2,
  abstract     = {The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X-axis phases and Y-axis phases (based on 2-D definition) can be used, rather than only the diagonal line. The large latency time inherited from Vernier structure is therefore dramatically reduced. The TDC is implemented in a 90nm CMOS process and consumes 1.8mA from 1.2V. The measured input range can safely cover a full period of a 50MHz sampling signal. With the same delay elements, the latency time is less than 1/6 of that needed in a standard Vernier TDC.},
  author       = {Lu, Ping and Andreani, Pietro and Liscidini, Antonio},
  isbn         = {978-1-4673-6059-3},
  issn         = {1529-2517},
  keyword      = {GRO,Vernier,Time to digital converter,2-D},
  language     = {eng},
  location     = {Seattle, Washington, United States},
  pages        = {151--154},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency},
  url          = {http://dx.doi.org/10.1109/RFIC.2013.6569547},
  year         = {2013},
}