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A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency

Lu, Ping LU ; Andreani, Pietro LU and Liscidini, Antonio (2013) In Analog Integrated Circuits and Signal Processing 76(2). p.195-206
Abstract
Abstract — The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X-axis phases and Y-axis phases (based on 2-D definition) can be used, rather than only the diagonal line. The large latency time inherited from Vernier structure is therefore dramatically reduced. The TDC is implemented in a 90nm CMOS process and consumes 1.8mA from 1.2V. The measured input range can safely cover a full period of a 50MHz sampling signal. With the same delay elements, the latency time is less than 1/6 of that needed in a standard Vernier TDC.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
GRO, Vernier, Time to digital converter, 2-D
in
Analog Integrated Circuits and Signal Processing
volume
76
issue
2
pages
195 - 206
publisher
Springer
external identifiers
  • wos:000322451700004
  • scopus:84881246409
ISSN
0925-1030
DOI
10.1007/s10470-013-0084-0
language
English
LU publication?
yes
id
295df13b-de09-4238-9e5c-77f107cd08da (old id 3800036)
alternative location
http://link.springer.com/article/10.1007/s10470-013-0084-0
date added to LUP
2013-05-28 11:13:30
date last changed
2019-04-30 10:44:31
@article{295df13b-de09-4238-9e5c-77f107cd08da,
  abstract     = {Abstract — The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X-axis phases and Y-axis phases (based on 2-D definition) can be used, rather than only the diagonal line. The large latency time inherited from Vernier structure is therefore dramatically reduced. The TDC is implemented in a 90nm CMOS process and consumes 1.8mA from 1.2V. The measured input range can safely cover a full period of a 50MHz sampling signal. With the same delay elements, the latency time is less than 1/6 of that needed in a standard Vernier TDC.},
  author       = {Lu, Ping and Andreani, Pietro and Liscidini, Antonio},
  issn         = {0925-1030},
  keyword      = {GRO,Vernier,Time to digital converter,2-D},
  language     = {eng},
  number       = {2},
  pages        = {195--206},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency},
  url          = {http://dx.doi.org/10.1007/s10470-013-0084-0},
  volume       = {76},
  year         = {2013},
}