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A GALS ASIC implementation from a CAL dataflow description

Prabhu, Hemanth LU ; Thomas, Sherine; Rodrigues, Joachim LU ; Olsson, Thomas and Carlsson, Anders (2011) 29th Norchip conference, 2011 In IEEE
Abstract
This paper presents low power hardware generation, based on a CAL actor language dataflow implementation. The CAL language gives a higher level of abstraction and generate both hardware and software description. The original CAL flow is targeted for hardware-software co-design of complex systems on FPGA. Modifications are done to the original CAL flow to facilitate low power ASIC implementations. The hardware-software co-design and Globally Asynchronous Locally Synchronous (GALS) design at a higher level of abstraction provides more freedom for design-space exploration and reduced design time. Performance is evaluated by a reference design, Orthogonal Frequency-Division Multiplexing (OFDM) multi-standard channel estimator based on robust... (More)
This paper presents low power hardware generation, based on a CAL actor language dataflow implementation. The CAL language gives a higher level of abstraction and generate both hardware and software description. The original CAL flow is targeted for hardware-software co-design of complex systems on FPGA. Modifications are done to the original CAL flow to facilitate low power ASIC implementations. The hardware-software co-design and Globally Asynchronous Locally Synchronous (GALS) design at a higher level of abstraction provides more freedom for design-space exploration and reduced design time. Performance is evaluated by a reference design, Orthogonal Frequency-Division Multiplexing (OFDM) multi-standard channel estimator based on robust Minimum Mean-Square Error (MMSE) algorithm. Higher throughput is attained due to inherent parallelism in CAL dataflow and reduced design time for GALS implementation. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Channel estimation, Clocks, Hardware, OFDM, Software, Synchronization, Throughput
in
IEEE
pages
4 pages
conference name
29th Norchip conference, 2011
external identifiers
  • Scopus:84856904729
ISBN
978-1-4577-0514-4
DOI
10.1109/NORCHP.2011.6126740
language
English
LU publication?
yes
id
7c969045-1d62-4d10-9b45-6044876fc3f6 (old id 2798078)
date added to LUP
2012-06-27 09:57:06
date last changed
2016-10-13 04:57:47
@misc{7c969045-1d62-4d10-9b45-6044876fc3f6,
  abstract     = {This paper presents low power hardware generation, based on a CAL actor language dataflow implementation. The CAL language gives a higher level of abstraction and generate both hardware and software description. The original CAL flow is targeted for hardware-software co-design of complex systems on FPGA. Modifications are done to the original CAL flow to facilitate low power ASIC implementations. The hardware-software co-design and Globally Asynchronous Locally Synchronous (GALS) design at a higher level of abstraction provides more freedom for design-space exploration and reduced design time. Performance is evaluated by a reference design, Orthogonal Frequency-Division Multiplexing (OFDM) multi-standard channel estimator based on robust Minimum Mean-Square Error (MMSE) algorithm. Higher throughput is attained due to inherent parallelism in CAL dataflow and reduced design time for GALS implementation.},
  author       = {Prabhu, Hemanth and Thomas, Sherine and Rodrigues, Joachim and Olsson, Thomas and Carlsson, Anders},
  isbn         = {978-1-4577-0514-4},
  keyword      = {Channel estimation,Clocks,Hardware,OFDM,Software,Synchronization,Throughput},
  language     = {eng},
  pages        = {4},
  series       = {IEEE},
  title        = {A GALS ASIC implementation from a CAL dataflow description},
  url          = {http://dx.doi.org/10.1109/NORCHP.2011.6126740},
  year         = {2011},
}