A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V-T Designs
(2013) IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) p.380-385- Abstract
- This paper proposes a process independent post layout de-synchronization flow implemented in tool command language working on designs operating in the sub-V-T regime. The overhead due to the self-timed operation is combated by introducing full-custom delay elements and latches for a standard 65-nm CMOS process. The flow offers the possibility to adjust granularity based on user requirements. Case studies with different reference designs manifested an average reduction of area and power overhead from 105% to 9% and 174% to 58% in comparison to a full standard cell de-synchronization approach.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4419034
- author
- Müller, Christoph LU ; Malkowsky, Steffen LU ; Andersson, Oskar LU ; Mohammadi, Babak LU ; Sparso, Jens and Rodrigues, Joachim LU
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
- pages
- 380 - 385
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
- conference dates
- 2013-10-07 - 2013-10-09
- external identifiers
-
- wos:000332046100078
- scopus:84899580503
- DOI
- 10.1109/VLSI-SoC.2013.6673313
- language
- English
- LU publication?
- yes
- id
- 98b022a9-0358-48a1-ab79-83f8d15449f7 (old id 4419034)
- date added to LUP
- 2016-04-04 10:17:30
- date last changed
- 2022-01-29 20:04:30
@inproceedings{98b022a9-0358-48a1-ab79-83f8d15449f7, abstract = {{This paper proposes a process independent post layout de-synchronization flow implemented in tool command language working on designs operating in the sub-V-T regime. The overhead due to the self-timed operation is combated by introducing full-custom delay elements and latches for a standard 65-nm CMOS process. The flow offers the possibility to adjust granularity based on user requirements. Case studies with different reference designs manifested an average reduction of area and power overhead from 105% to 9% and 174% to 58% in comparison to a full standard cell de-synchronization approach.}}, author = {{Müller, Christoph and Malkowsky, Steffen and Andersson, Oskar and Mohammadi, Babak and Sparso, Jens and Rodrigues, Joachim}}, booktitle = {{2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)}}, language = {{eng}}, pages = {{380--385}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V-T Designs}}, url = {{http://dx.doi.org/10.1109/VLSI-SoC.2013.6673313}}, doi = {{10.1109/VLSI-SoC.2013.6673313}}, year = {{2013}}, }