Oskar Andersson (Former)
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- 2018
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Mark
A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28 nm FD–SOI
(
- Contribution to journal › Article
- 2017
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Mark
Logic filter cache for wide-VDD-range processors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2016
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Mark
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS
(
- Contribution to journal › Article
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Mark
Ultra-low Voltage Embedded Memories – Design Aspects and a Biomedical Use-case
2016)(
- Thesis › Doctoral thesis (compilation)
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Mark
A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI
2016) European Solid-State Circuits Conference (ESSCIRC). 2016(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Improving practical sensitivity of energy optimized wake-up receivers : Proof of concept in 65nm CMOS
(
- Contribution to journal › Article
- 2015
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Mark
A 290mV sub-VT ASIC for Real-Time Atrial Fibrillation Detection
(
- Contribution to journal › Article
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Mark
Reconfigurable and Selectively-Adaptive Signal Processing for Multi-Mode Wireless Communication
2015) SiPS(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 400 mV Atrial Fibrillation Detector with 0.56 pJ/Operation in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding