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A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28 nm FD–SOI

Mohammadi, Babak LU ; Andersson, Oskar LU ; Nguyen, Joseph; Ciampolini, Lorenzo; Cathelin, Andreia and Rodrigues, Joachim LU (2017) In IEEE Transactions on Circuits and Systems I: Regular Papers
Abstract
A 128kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in 28 nm FD–SOI technology is presented. An ideal power management scenario in a single supply system is achieved by permanently keeping the storage elements in the vicinity of the retention voltage. Performance and reliability is regained by boosting the voltage on critical nodes. The cost of voltage boost generation unit is minimized by 66 low-power and area efficient on-chip charge
pumps, i.e., 64 for boosting the voltages on write-bitlines and 2 for the wordlines. The charge pump energy overhead is reduced by introducing a new boost paradigm with an on-demand activation mechanism that generates the required boost level in a single clock cycle. A... (More)
A 128kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in 28 nm FD–SOI technology is presented. An ideal power management scenario in a single supply system is achieved by permanently keeping the storage elements in the vicinity of the retention voltage. Performance and reliability is regained by boosting the voltage on critical nodes. The cost of voltage boost generation unit is minimized by 66 low-power and area efficient on-chip charge
pumps, i.e., 64 for boosting the voltages on write-bitlines and 2 for the wordlines. The charge pump energy overhead is reduced by introducing a new boost paradigm with an on-demand activation mechanism that generates the required boost level in a single clock cycle. A sense amplifier-less read architecture enables a reliable and high performance read operation. Measurements identify several meritorious metrics. The minimum read energy is identified as 8.4fJ/bit-access, achieved for 90 MHz operation at
0.3 V. Furthermore, the minimum operating voltage is measured
as 240 mV, and data is retained in ultra-low voltage regime,
ranging down to 0.2V. The bitcell area, implemented using
standard design rules, is 0.261µm2. The entire memory, including
the digital test circuitry, occupies 0.161 mm2 of chip area. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
epub
subject
keywords
ULV SRAM, 7T bitcell, Tree decoder, single cycle boost
in
IEEE Transactions on Circuits and Systems I: Regular Papers
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85030684389
ISSN
1549-8328
DOI
10.1109/TCSI.2017.2750762
language
English
LU publication?
yes
id
79bdc96e-3ae8-4ae6-ab6e-4a72d179be98
date added to LUP
2017-09-15 14:33:15
date last changed
2018-01-07 12:18:50
@article{79bdc96e-3ae8-4ae6-ab6e-4a72d179be98,
  abstract     = {A 128kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in 28 nm FD–SOI technology is presented. An ideal power management scenario in a single supply system is achieved by permanently keeping the storage elements in the vicinity of the retention voltage. Performance and reliability is regained by boosting the voltage on critical nodes. The cost of voltage boost generation unit is minimized by 66 low-power and area efficient on-chip charge<br/>pumps, i.e., 64 for boosting the voltages on write-bitlines and 2 for the wordlines. The charge pump energy overhead is reduced by introducing a new boost paradigm with an on-demand activation mechanism that generates the required boost level in a single clock cycle. A sense amplifier-less read architecture enables a reliable and high performance read operation. Measurements identify several meritorious metrics. The minimum read energy is identified as 8.4fJ/bit-access, achieved for 90 MHz operation at<br/>0.3 V. Furthermore, the minimum operating voltage is measured<br/>as 240 mV, and data is retained in ultra-low voltage regime,<br/>ranging down to 0.2V. The bitcell area, implemented using<br/>standard design rules, is 0.261µm2. The entire memory, including<br/>the digital test circuitry, occupies 0.161 mm2 of chip area.},
  author       = {Mohammadi, Babak and Andersson, Oskar and Nguyen, Joseph and Ciampolini, Lorenzo and Cathelin, Andreia and Rodrigues, Joachim},
  issn         = {1549-8328},
  keyword      = {ULV SRAM,7T bitcell,Tree decoder,single cycle boost},
  language     = {eng},
  month        = {08},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Circuits and Systems I: Regular Papers},
  title        = {A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28 nm FD–SOI},
  url          = {http://dx.doi.org/10.1109/TCSI.2017.2750762},
  year         = {2017},
}