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Ultra-low Power Design Approaches in Memories and Assist Techniques

Mohammadi, Babak LU (2017)
Abstract
The need for more functionality and higher performance has increased the number of transistors to billions in current processors. A high number of transistors on the same chip area increases the power density, which in turn heats up the devices and lowers the life time of batteries. The increasing demand for devices relying on battery and harvested energies in the Internet of Things (IoT) era has turned the energy efficiency to a main concern and challenge in the silicon industry. Down-scaling the supply voltage is the most effective method for reducing the energy dissipation, and many applications’ minimum energy point is placed at sub- or near-threshold operation region. However, down-scaling the voltage worsens the performance and... (More)
The need for more functionality and higher performance has increased the number of transistors to billions in current processors. A high number of transistors on the same chip area increases the power density, which in turn heats up the devices and lowers the life time of batteries. The increasing demand for devices relying on battery and harvested energies in the Internet of Things (IoT) era has turned the energy efficiency to a main concern and challenge in the silicon industry. Down-scaling the supply voltage is the most effective method for reducing the energy dissipation, and many applications’ minimum energy point is placed at sub- or near-threshold operation region. However, down-scaling the voltage worsens the performance and noise-immunity of the circuits which need to be addressed at
different design levels.
On-chip memories are among the main building blocks in digital circuits, where their area and energy is often a dominating factor, and consequently, increasing their area and power efficiency is of vital importance. There are numerous on-chip memory categories which serve different design requirements. Standard-cell based memories are known to be highly configurable and voltage scalable, however, they are area inefficient for large memory capacities. On the other hand, the conventional Static Random Access Memory (SRAM) is relatively more area efficient for large capacities, however, it has a limited voltage scaling range which in turn, poses a high energy cost to the system.
The main focus of this thesis is on memory power reduction techniques at different abstraction levels from transistor to architectural level. By designing a custom memory-cell, the capacity range in which standard-cell based memories have a higher area efficiency is extended, and a detailed trade off discussion between energy, performance and area is provided. For memories with larger capacities, a low-power SRAM architecture has been designed which is able to operate in the Ultra-Low Voltage (ULV) regime. The performance and reliability is increased by using voltage assist techniques which boost the critical nodes during write and read accesses. Boosted voltages are generated locally by using on-chip charge pumps which are operational in the deep subthreshold regime. Performance, area, and energy efficiency were the main focus in the charge pump realization to maintain the low-power profile of the system. To avoid a continuous charge pump activation, a new charge pumping mechanism has been introduced which generates the required voltage level instantly at a low area cost. This effectively reduces the dynamic energy cost of the system and facilitates the application of a small and low cost charge pump. To
increase the voltage scalability of the SRAM, a hybrid read architecture has been proposed. This method avoids the voltage limitation of sense-amplifiers and provides a higher performance at ULV with extremely low energy cost. Moreover, to facilitate a reliable communication between design blocks operating at different voltage domains in an SoC, a low-power and area efficient level shifter is introduced and its properties are studied and measured. Finally, it is shown that without paying high area and energy penalties, all design constraints can be met by: a) selecting an architecture with respect to the structure and nature of a design, and, b) realizing the best matching architectures for the required blocks and optimizing them at all design levels. (Less)
Please use this url to cite or link to this publication:
author
supervisor
opponent
  • Professor Aunet, Snorre, Norwegian University of Science and Technology (NTNU), Norway
organization
publishing date
type
Thesis
publication status
submitted
subject
keywords
Memory, SRAM, assist technique, charge pump, ULP, ULV
pages
186 pages
publisher
Department of Electrical and Information Technology, Lund University
defense location
E:1406, E-huset, Ole Römers väg 3, Lund University, Faculty of Engineering.
defense date
2017-06-16 10:15
ISBN
978-91-7753-178-4
language
English
LU publication?
yes
id
95956fa0-793e-4577-bff6-6baa20fd0ab5
date added to LUP
2017-05-22 12:05:39
date last changed
2017-05-23 13:53:16
@phdthesis{95956fa0-793e-4577-bff6-6baa20fd0ab5,
  abstract     = {The need for more functionality and higher performance has increased the number of transistors to billions in current processors. A high number of transistors on the same chip area increases the power density, which in turn heats up the devices and lowers the life time of batteries. The increasing demand for devices relying on battery and harvested energies in the Internet of Things (IoT) era has turned the energy efficiency to a main concern and challenge in the silicon industry. Down-scaling the supply voltage is the most effective method for reducing the energy dissipation, and many applications’ minimum energy point is placed at sub- or near-threshold operation region. However, down-scaling the voltage worsens the performance and noise-immunity of the circuits which need to be addressed at<br/>different design levels. <br/>On-chip memories are among the main building blocks in digital circuits, where their area and energy is often a dominating factor, and consequently, increasing their area and power efficiency is of vital importance. There are numerous on-chip memory categories which serve different design requirements. Standard-cell based memories are known to be highly configurable and voltage scalable, however, they are area inefficient for large memory capacities. On the other hand, the conventional Static Random Access Memory (SRAM) is relatively more area efficient for large capacities, however, it has a limited voltage scaling range which in turn, poses a high energy cost to the system. <br/>The main focus of this thesis is on memory power reduction techniques at different abstraction levels from transistor to architectural level. By designing a custom memory-cell, the capacity range in which standard-cell based memories have a higher area efficiency is extended, and a detailed trade off discussion between energy, performance and area is provided. For memories with larger capacities, a low-power SRAM architecture has been designed which is able to operate in the Ultra-Low Voltage (ULV) regime. The performance and reliability is increased by using voltage assist techniques which boost the critical nodes during write and read accesses. Boosted voltages are generated locally by using on-chip charge pumps which are operational in the deep subthreshold regime. Performance, area, and energy efficiency were the main focus in the charge pump realization to maintain the low-power profile of the system. To avoid a continuous charge pump activation, a new charge pumping mechanism has been introduced which generates the required voltage level instantly at a low area cost. This effectively reduces the dynamic energy cost of the system and facilitates the application of a small and low cost charge pump. To<br/>increase the voltage scalability of the SRAM, a hybrid read architecture has been proposed. This method avoids the voltage limitation of sense-amplifiers and provides a higher performance at ULV with extremely low energy cost. Moreover, to facilitate a reliable communication between design blocks operating at different voltage domains in an SoC, a low-power and area efficient level shifter is introduced and its properties are studied and measured. Finally, it is shown that without paying high area and energy penalties, all design constraints can be met by: a) selecting an architecture with respect to the structure and nature of a design, and, b) realizing the best matching architectures for the required blocks and optimizing them at all design levels.},
  author       = {Mohammadi, Babak},
  isbn         = {978-91-7753-178-4},
  keyword      = {Memory,SRAM,assist technique,charge pump,ULP,ULV},
  language     = {eng},
  month        = {06},
  pages        = {186},
  publisher    = {Department of Electrical and Information Technology, Lund University},
  school       = {Lund University},
  title        = {Ultra-low Power Design Approaches in Memories and Assist Techniques},
  year         = {2017},
}