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A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter

Mohammadi, Babak LU and Rodrigues, Joachim LU (2014) IEEE International Symposium on Circuits and Systems (ISCAS), 2014 p.990-993
Abstract
A conventional level-shifter is modified to extend the operation range down to subthreshold regime. Leakage current is reduced by utilizing transistor stacking, channel stretching, and reverse body biasing. The design has a standard-cell compliant layout and is fully integrated in a conventional digital design flow. The level-shifter is manufactured in 65 nm CMOS, and functionality is verified by measurements. The proposed design is capable of converting 0.12 to 1.2 V in a single stage, and has a static power consumption of 640 pW at a 0.12 to 1 V conversion. The minimum energy/cycle of 28 fJ/cycle with a conversion speed of 72 MHz was observed at 0.3 to 1 V conversion.
Please use this url to cite or link to this publication:
author
and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
level-converter, level-shifter, ULV, ultra low power, ultra low voltage, single stage
host publication
2014 IEEE International Symposium on Circuits and Systems (ISCAS)
pages
990 - 993
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2014
conference location
Melbourne, Australia
conference dates
2014-06-01 - 2014-06-05
external identifiers
  • wos:000346488600252
  • scopus:84907420334
ISSN
0271-4310
2158-1525
language
English
LU publication?
yes
id
46847acb-c2c2-40ed-9a8f-851eed9dc97d (old id 5091485)
date added to LUP
2016-04-01 10:51:09
date last changed
2025-10-14 11:27:03
@inproceedings{46847acb-c2c2-40ed-9a8f-851eed9dc97d,
  abstract     = {{A conventional level-shifter is modified to extend the operation range down to subthreshold regime. Leakage current is reduced by utilizing transistor stacking, channel stretching, and reverse body biasing. The design has a standard-cell compliant layout and is fully integrated in a conventional digital design flow. The level-shifter is manufactured in 65 nm CMOS, and functionality is verified by measurements. The proposed design is capable of converting 0.12 to 1.2 V in a single stage, and has a static power consumption of 640 pW at a 0.12 to 1 V conversion. The minimum energy/cycle of 28 fJ/cycle with a conversion speed of 72 MHz was observed at 0.3 to 1 V conversion.}},
  author       = {{Mohammadi, Babak and Rodrigues, Joachim}},
  booktitle    = {{2014 IEEE International Symposium on Circuits and Systems (ISCAS)}},
  issn         = {{0271-4310}},
  keywords     = {{level-converter; level-shifter; ULV; ultra low power; ultra low voltage; single stage}},
  language     = {{eng}},
  pages        = {{990--993}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter}},
  year         = {{2014}},
}