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- 2014
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Mark
Energy Efficient SQRD Processor for LTE-A using a Group-sort Update Scheme
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Hardware Efficient Approximative Matrix Inversion for Linear Pre-Coding in Massive MIMO
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 1-1 MASH 2-D Vernier Time-to-Digital Converter with 2nd-order noise shaping
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Analog and Digital Approaches for an Energy Efficient Low Complexity Channel Decoder
2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013 In Proceedings - IEEE International Symposium on Circuits and Systems p.1564-1567(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
High-Throughput Hardware-Efficient Soft-Input Soft-Output MIMO Detector for Iterative Receivers
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding