Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm
(2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013 p.293-296- Abstract
- In LTE base-stations, RoHC is a processingintensive
algorithm that may limit the system from serving a
large number of users when it is used to compress the VoIP
packets of mobile traffic. In this paper, a hardware-software and a
full-hardware solution are proposed to accelerate the RoHC compression
algorithm in LTE base-stations and enhance the system
throughput and capacity. Results for both solutions are discussed
and compared with respect to design metrics like throughput,
capacity, power consumption, and hardware resources. This
comparison is instrumental in taking architectural level trade-off
decisions in-order to meet the present day... (More) - In LTE base-stations, RoHC is a processingintensive
algorithm that may limit the system from serving a
large number of users when it is used to compress the VoIP
packets of mobile traffic. In this paper, a hardware-software and a
full-hardware solution are proposed to accelerate the RoHC compression
algorithm in LTE base-stations and enhance the system
throughput and capacity. Results for both solutions are discussed
and compared with respect to design metrics like throughput,
capacity, power consumption, and hardware resources. This
comparison is instrumental in taking architectural level trade-off
decisions in-order to meet the present day requirements and also
be ready to support a future evolution. In terms of throughput,
a gain of 20% (6250 packets/sec) is achieved in the HW-SW
implementation by accelerating the Cyclic Redundancy Check
(CRC) and the Least Significant Bit (LSB) encoding in hardware.
The full-HW implementation leads to a throughput of 45 times
(244000 packets/sec) compared to the SW-Only implementation.
The full-HW solution consumes more Adaptive Look-Up Tables
(7477 ALUTs) compared to the HW-SW solution (2614 ALUTs)
when synthesized on Altera’s Arria II GX FPGA. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3359438
- author
- Al-Obaidi, Mohammed ; Kittur, Harshavardhan ; Andersson, Håkan and Öwall, Viktor LU
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2013 IEEE International Symposium on Circuits and Systems (ISCAS)
- pages
- 4 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Symposium on Circuits and Systems (ISCAS), 2013
- conference location
- Beijing, China
- conference dates
- 2013-05-19 - 2013-05-23
- external identifiers
-
- wos:000332006800074
- scopus:84883331261
- ISSN
- 2158-1525
- 0271-4310
- ISBN
- 978-1-4673-5762-3
- 978-1-4673-5760-9
- DOI
- 10.1109/ISCAS.2013.6571840
- project
- EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
- language
- English
- LU publication?
- yes
- id
- 6647228a-2b24-4a51-9e2a-e5eba4707efa (old id 3359438)
- date added to LUP
- 2016-04-01 09:48:34
- date last changed
- 2024-01-06 00:28:04
@inproceedings{6647228a-2b24-4a51-9e2a-e5eba4707efa,
abstract = {{In LTE base-stations, RoHC is a processingintensive<br/><br>
algorithm that may limit the system from serving a<br/><br>
large number of users when it is used to compress the VoIP<br/><br>
packets of mobile traffic. In this paper, a hardware-software and a<br/><br>
full-hardware solution are proposed to accelerate the RoHC compression<br/><br>
algorithm in LTE base-stations and enhance the system<br/><br>
throughput and capacity. Results for both solutions are discussed<br/><br>
and compared with respect to design metrics like throughput,<br/><br>
capacity, power consumption, and hardware resources. This<br/><br>
comparison is instrumental in taking architectural level trade-off<br/><br>
decisions in-order to meet the present day requirements and also<br/><br>
be ready to support a future evolution. In terms of throughput,<br/><br>
a gain of 20% (6250 packets/sec) is achieved in the HW-SW<br/><br>
implementation by accelerating the Cyclic Redundancy Check<br/><br>
(CRC) and the Least Significant Bit (LSB) encoding in hardware.<br/><br>
The full-HW implementation leads to a throughput of 45 times<br/><br>
(244000 packets/sec) compared to the SW-Only implementation.<br/><br>
The full-HW solution consumes more Adaptive Look-Up Tables<br/><br>
(7477 ALUTs) compared to the HW-SW solution (2614 ALUTs)<br/><br>
when synthesized on Altera’s Arria II GX FPGA.}},
author = {{Al-Obaidi, Mohammed and Kittur, Harshavardhan and Andersson, Håkan and Öwall, Viktor}},
booktitle = {{2013 IEEE International Symposium on Circuits and Systems (ISCAS)}},
isbn = {{978-1-4673-5762-3}},
issn = {{2158-1525}},
language = {{eng}},
pages = {{293--296}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm}},
url = {{http://dx.doi.org/10.1109/ISCAS.2013.6571840}},
doi = {{10.1109/ISCAS.2013.6571840}},
year = {{2013}},
}