A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
(2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013 p.169-172- Abstract
- This paper presents a 1MHz bandwidth, ΔƩ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔƩ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping signals to decrease the charge mismatch. Therefore, a wide loop bandwidth can be obtained while keeping reasonable performance of out-of-band phase noise. The proposed synthesizer is simulated in 90nm CMOS process, consuming 20.96mA from a 1 V supply.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3350492
- author
- Ye, Dawei ; Lu, Ping LU ; Andreani, Pietro LU and Zee, Ronan van der
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- [Host publication title missing]
- pages
- 169 - 172
- publisher
- ISCAS
- conference name
- IEEE International Symposium on Circuits and Systems (ISCAS), 2013
- conference location
- Beijing, China
- conference dates
- 2013-05-19 - 2013-05-23
- external identifiers
-
- wos:000332006800043
- ISSN
- 0271-4310
- 2158-1525
- language
- English
- LU publication?
- yes
- id
- 9c142e64-ba80-49df-9176-93610bae7a53 (old id 3350492)
- alternative location
- http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6571809
- date added to LUP
- 2016-04-01 10:38:02
- date last changed
- 2019-04-30 11:07:16
@inproceedings{9c142e64-ba80-49df-9176-93610bae7a53, abstract = {{This paper presents a 1MHz bandwidth, ΔƩ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔƩ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping signals to decrease the charge mismatch. Therefore, a wide loop bandwidth can be obtained while keeping reasonable performance of out-of-band phase noise. The proposed synthesizer is simulated in 90nm CMOS process, consuming 20.96mA from a 1 V supply.}}, author = {{Ye, Dawei and Lu, Ping and Andreani, Pietro and Zee, Ronan van der}}, booktitle = {{[Host publication title missing]}}, issn = {{0271-4310}}, language = {{eng}}, pages = {{169--172}}, publisher = {{ISCAS}}, title = {{A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing}}, url = {{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6571809}}, year = {{2013}}, }