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A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI

Mohammadi, Babak LU ; Andersson, Oskar LU ; Nguyen, Joseph; Ciampolini, Lorenzo; Cathelin, Andreia and Rodrigues, Joachim LU (2016) European Solid-State Circuits Conference (ESSCIRC). 2016 In European Solid-State Circuits Conference (ESSCIRC), 2016
Abstract
In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90 MHz read speed at 300 mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240 mV and the retention voltage is found at 200 mV.
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
European Solid-State Circuits Conference (ESSCIRC), 2016
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
European Solid-State Circuits Conference (ESSCIRC). 2016
external identifiers
  • scopus:84994476444
DOI
10.1109/ESSCIRC.2016.7598333
language
English
LU publication?
yes
id
0464838f-343f-4fde-aa04-94af04369124
date added to LUP
2016-08-29 16:34:22
date last changed
2017-07-23 05:17:18
@inproceedings{0464838f-343f-4fde-aa04-94af04369124,
  abstract     = {In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90 MHz read speed at 300 mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240 mV and the retention voltage is found at 200 mV. },
  author       = {Mohammadi, Babak and Andersson, Oskar and Nguyen, Joseph and Ciampolini, Lorenzo and Cathelin, Andreia and Rodrigues, Joachim},
  booktitle    = { European Solid-State Circuits Conference (ESSCIRC), 2016},
  language     = {eng},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI},
  url          = {http://dx.doi.org/10.1109/ESSCIRC.2016.7598333},
  year         = {2016},
}