Oskar Andersson (Former)
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- 2018
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Mark
A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28 nm FD–SOI
(
- Contribution to journal › Article
- 2017
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Mark
An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Logic filter cache for wide-VDD-range processors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2016
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Mark
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS
(
- Contribution to journal › Article
-
Mark
Improving practical sensitivity of energy optimized wake-up receivers : Proof of concept in 65nm CMOS
(
- Contribution to journal › Article
-
Mark
Ultra-low Voltage Embedded Memories – Design Aspects and a Biomedical Use-case
2016)(
- Thesis › Doctoral thesis (compilation)
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Mark
A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI
2016) European Solid-State Circuits Conference (ESSCIRC). 2016(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2015
-
Mark
A 290mV sub-VT ASIC for Real-Time Atrial Fibrillation Detection
(
- Contribution to journal › Article
-
Mark
A 400 mV Atrial Fibrillation Detector with 0.56 pJ/Operation in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Reconfigurable and Selectively-Adaptive Signal Processing for Multi-Mode Wireless Communication
2015) SiPS(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
A 35 fJ/bit-access Sub-VT Memory Using a Dual-Bit Area-Optimized Standard-cell in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
2014) FTFC(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Dual-VT 4kb Sub-VT Memories with <1 pW/bit Leakage in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V-T Designs
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
IR-Drop Reduction in Sub-VT Circuits by De-synchronization
2012) IEEE Subthreshold Microelectronics Conference, IEEE-Sub-Vt 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Integration of Full-Custom Cells in a Standard-Cell Based Flow
2012) CDNLive! EMEA, 2012(
- Contribution to conference › Paper, not in proceeding
- 2011
-
Mark
Synthesis Strategies for Sub-VT Systems
2011) 20th European Conference on Circuit Theory and Design. ECCTD 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Impact of switching activity on the energy minimum voltage for 65 nm Sub-VT CMOS
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Low Power and Area Efficient Implementation of a Real-Time AF Detection Algorithm in 130 nm CMOS
2011) Swedish System-on-Chip Conference, SSoCC 2011(
- Contribution to conference › Paper, not in proceeding