Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS
(2013) Swedish System-On-Chip Conference (SSoCC), 2013- Abstract
- Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub- VT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D- latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power... (More)
- Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub- VT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D- latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220mV) and a total energy of 14fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65 nm CMOS reported to date. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3812707
- author
- Andersson, Oskar LU ; Meinerzhagen, Pascal ; Mohammadi, Babak LU ; Sherazi, Syed Muhammad Yasser LU ; Burg, Andreas and Rodrigues, Joachim LU
- organization
- publishing date
- 2013
- type
- Contribution to conference
- publication status
- published
- subject
- conference name
- Swedish System-On-Chip Conference (SSoCC), 2013
- conference location
- Ystad, Sweden
- conference dates
- 2013-05-06 - 2013-05-07
- language
- English
- LU publication?
- yes
- id
- a549186f-1458-43d5-9487-53e73e271868 (old id 3812707)
- date added to LUP
- 2016-04-04 13:34:38
- date last changed
- 2018-11-21 21:14:53
@misc{a549186f-1458-43d5-9487-53e73e271868, abstract = {{Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub- VT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D- latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220mV) and a total energy of 14fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65 nm CMOS reported to date.}}, author = {{Andersson, Oskar and Meinerzhagen, Pascal and Mohammadi, Babak and Sherazi, Syed Muhammad Yasser and Burg, Andreas and Rodrigues, Joachim}}, language = {{eng}}, title = {{Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS}}, year = {{2013}}, }