Oskar Andersson (Former)
11 – 20 of 23
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=" "
width=" "
height=" "
allowtransparency="true"
frameborder="0">
</iframe>
- 2014
-
Mark
A 35 fJ/bit-access Sub-VT Memory Using a Dual-Bit Area-Optimized Standard-cell in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
2014) FTFC(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Dual-VT 4kb Sub-VT Memories with <1 pW/bit Leakage in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V-T Designs
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
IR-Drop Reduction in Sub-VT Circuits by De-synchronization
2012) IEEE Subthreshold Microelectronics Conference, IEEE-Sub-Vt 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Integration of Full-Custom Cells in a Standard-Cell Based Flow
2012) CDNLive! EMEA, 2012(
- Contribution to conference › Paper, not in proceeding