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A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS

Meraji, Reza LU ; Anderson, John B LU ; Sjöland, Henrik LU and Öwall, Viktor LU (2013) 2013 IEEE International Conference on Electronics, Circuits, and Systems In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS) p.349-352
Abstract
Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)(8) convolutional codes and takes 0.104 mm(2) on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 W the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip... (More)
Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)(8) convolutional codes and takes 0.104 mm(2) on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 W the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver. (Less)
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)
pages
349 - 352
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
2013 IEEE International Conference on Electronics, Circuits, and Systems
external identifiers
  • WOS:000339725900096
ISBN
978-1-4799-2452-3
language
English
LU publication?
yes
id
ecddb403-a9cc-4417-8c3b-710309555350 (old id 4668171)
date added to LUP
2014-09-24 14:30:27
date last changed
2016-04-16 07:27:21
@misc{ecddb403-a9cc-4417-8c3b-710309555350,
  abstract     = {Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)(8) convolutional codes and takes 0.104 mm(2) on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 W the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver.},
  author       = {Meraji, Reza and Anderson, John B and Sjöland, Henrik and Öwall, Viktor},
  isbn         = {978-1-4799-2452-3},
  language     = {eng},
  pages        = {349--352},
  publisher    = {ARRAY(0x7d99d00)},
  series       = {2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)},
  title        = {A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS},
  year         = {2013},
}