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A low-complexity method for distributed clocking on digital ASICs

Olsson, Thomas LU and Nilsson, Peter LU (2004) Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits In Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (IEEE Cat. No.04EX909) p.344-347
Abstract
A low-complexity method using synchronous wrappers is proposed to simplify communication between modules using unsynchronized clocks. To test the method, it is implemented together with a divider and an FFT co-processor. The divider with synchronous wrapper and local clock generator, delivering a 500 MHz clock, is synthesized and verified using post-synthesis simulations for a 0.18 μm 1.8 V CMOS technology. A complete description of the wrapper in synthesizable VHDL-code including local a local clock generator makes the method portable between technologies
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
local clock generator, divider, FFT coprocessor, unsynchronized clocks, digital ASIC, synchronous wrappers, distributed clocking, low-complexity method, CMOS technology, post-synthesis simulation, VHDL-code, large SoC, 1.8 V
in
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (IEEE Cat. No.04EX909)
pages
344 - 347
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
external identifiers
  • WOS:000224435400072
  • Scopus:14544277111
ISBN
0-7803-8637-X
DOI
10.1109/APASIC.2004.1349492
language
English
LU publication?
yes
id
3b38104b-43d3-4fb4-8537-a9695da7ed1f (old id 614749)
date added to LUP
2007-12-04 12:44:15
date last changed
2016-10-13 04:44:57
@misc{3b38104b-43d3-4fb4-8537-a9695da7ed1f,
  abstract     = {A low-complexity method using synchronous wrappers is proposed to simplify communication between modules using unsynchronized clocks. To test the method, it is implemented together with a divider and an FFT co-processor. The divider with synchronous wrapper and local clock generator, delivering a 500 MHz clock, is synthesized and verified using post-synthesis simulations for a 0.18 μm 1.8 V CMOS technology. A complete description of the wrapper in synthesizable VHDL-code including local a local clock generator makes the method portable between technologies},
  author       = {Olsson, Thomas and Nilsson, Peter},
  isbn         = {0-7803-8637-X},
  keyword      = {local clock generator,divider,FFT coprocessor,unsynchronized clocks,digital ASIC,synchronous wrappers,distributed clocking,low-complexity method,CMOS technology,post-synthesis simulation,VHDL-code,large SoC,1.8 V},
  language     = {eng},
  pages        = {344--347},
  publisher    = {ARRAY(0x8e918c0)},
  series       = {Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (IEEE Cat. No.04EX909)},
  title        = {A low-complexity method for distributed clocking on digital ASICs},
  url          = {http://dx.doi.org/10.1109/APASIC.2004.1349492},
  year         = {2004},
}