Customized Processor Design for 5G Data Link Layer Processing

Abstract

This thesis aims to explore the workflow related to designing an application specific instruction-set processor (ASIP). An ASIP is a processor similar to a hardware accelerator (HAC) in terms of performance and efficiency, but containing elements of general purpose processors (GPPs) when it comes to programmability and flexibility. The thesis centers around the design of an ASIP which will handle layer-2 processing in the 5G uplink i.e. keeping track of resources that are used by the user-equipment (UE) device. The ASIP and its related workflow are a relatively new concept in the wireless communications field; historically the large phone manufacturers have bought or licensed intellectual property (IP) from large chip designers such as ARM or Qualcomm, and then designed their applications around the framework that these chipsets provide. The main driving factor behind this exploration of the ASIP as a competitor to the GPP and the HAC is the relative maturity of design tools and the need for ever smaller devices, where efficiency in both power and size while keeping performance high is of utmost importance. Along with greater efficiency, today’s devices are also often required to have some sort of design flexibility to facilitate changing standards or device usage cases. The design tool chosen for use in this thesis is Codasip Studio, which has a
workflow similar to other chipset design tools: a description of the architecture and it’s instruction set architecture (ISA) is constructed, then after testing this behavioural representation it is sequentialized into the pipeline model and simulated. The final step is testing the firmware and peripherals on the simulated processor, before a VHDL or Verilog design is generated by the tool ready to export for register-transfer level (RTL) synthesis. The ASIP in this thesis is designed to run
seven tasks which it switches between depending on what type of data processing is required or available at the moment. The design finalized in the thesis contains three tasks that are completely implemented and one task that is partially completed but not synthesized in RTL. The assumption that the remaining tasks have a similar complexity means that the results can be extrapolated to give an approximation of the entire processor. The total number of implemented instructions is 88. Of these 88 instructions, 55 are ASIs and 33 are part of the base instruction set, the set needed for the processor to be Turing complete, and therefore able to act as a GPP. The synthesized ASIP design is compared to several ARM equivalents
in power consumption, area usage and instruction efficiency; the amount of
instructions that are needed to complete the test firmware loop. The results prove that the ASIP is a superior choice to the other processors, in this specific use case, by providing much higher throughput at roughly the same power consumption and area usage. In regards to the HAC comparison, no data was available to compare with in this specific case, so the comparison in this thesis is mostly a subjective one in regard to the design process.

Popular Abstract

How do you design a processor today? When you think of the processor in your mobile phone, what tasks does it have to perform? Should it be able to run all your applications as well as handle network communication, or should it only run certain specific tasks, and how would the specific tasks impact the size and power consumed by the processor? There are many different approaches to this design problem, in previous generations of mobile networking standards, phone companies have often used general purpose processors (GPPs) for the network communication processing. A GPP is a processor designed to work sufficiently for a wide array of different applications, while generally not excelling at any single task. This is an
inefficiency that becomes problematic in 5G, where performance and low power consumption are more important than ever. What if the company that designed the software instead decided to build a processor tailored exactly to the needs it had?
The flexibility of a processor is often defined by it’s programmability i.e. how much can it’s functionality be changed after it is in the final product. General purpose processors are generally the most flexible and dedicated hardware such as hardware accelerators (HAC) the least. Holding the middle ground between the two are application specific instruction-set processors (ASIPs); which are able to move closer to either of the former depending on the needs of the design. To design an ASIP efficiently there needs to be a clear idea of what kind of task it should perform, since the physical form of the processor will change depending on what it should do. When this is decided, a design tool is needed to create a model of the processor, which can then in turn be used by other tools to provide the
final physical description of the processor. If the tool used is well designed it can significantly speed up the process and provide the user with useful information and means to test the design without having to physically construct it. One such tool is Codasip Studio, and when it is used together with it’s own language to describe an ASIP; it gives area and power consumption results very similar to current advanced GPPs with the added benefit of the ASIP being much more efficient at performing the specific task it is designed for. If a similar tool was used to design
an HAC for the same application, the performance results might be a bit better, but it’s behaviour would also not be able to be changed after the fact. That is the most compelling thing about ASIPs, they can be designed to be exactly as flexible as needed so no part of the processor is wasted or superfluous. Design tools such as Codasip Studio enable simplifications in the development process which make it faster and easier to use than traditional development methods.

• author: Wargéus, Patric and Forsberg, Lukas
• supervisor: Joachim Rodrigues
• organization: Department of Electrical and Information Technology
• course: EITM01 20201
• year: 2020
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• report number: LU/LTH-EIT 2020-784
• language: English
• id: 9029118
• date added to LUP: 2020-09-16 10:59:34
• date last changed: 2020-09-16 10:59:34