Design and implementation of testable fault-tolerant RISC-V system

Abstract

This thesis aims to investigate and implement a fault-tolerant energy-efficient

RISC-V based system on chip (SoC). Key features of the SoC is the testabil-
ity and reliability of the low power on-chip embedded memories. A built-in self-
test (BIST) for the on-chip memories has been designed and implemented to run

on-demand diagnostic tests to detect manufacturing errors in the memories. It
incorporates three different algorithms to test for common manufacturing memory
faults. Runtime soft errors are detected and corrected using an error correction
code unit (ECC), which can correct up to two errors. The ECC is integrated with
the RISC-V core and memories to increase the fault-tolerance of the SoC at low
voltages. The ECC components importance increases as the probability of soft
errors increase with lowering of the supply voltage. Power savings up to 46% for
the entire system was simulated when the supply voltage was decreased from 1.2V
down to 0.8V. The addition of the ECC components resulted in a 3.5% core area
increase. The integrated memory built-in self-test contributed to another 24.4%
area increase of the core.

Popular Abstract

Improved semiconductor manufacturing processes and techniques have paved the
way for the development of more complex and power-efficient integrated circuits.
The higher achievable transistor density enables more functionality to be packed
into the same circuit die than before. These advanced computational circuits are
embedded in all handheld electronic devices and the internet of things that are

present in our day to day life. Higher transistor density combined with high con-
sumer demands on battery lifetime and functionality requirements creates difficult

challenges in the development phase of these circuits. As the complexity increases
the risk of manufacturing process variations is more likely to affect the system
functionality. Fault-tolerant and error detection techniques can be incorporated
into the system to counteract the effect of these potential manufacturing errors.
As the systems get more complex over time, the task of conducting tests and
diagnostic evaluation of the chips grow. Typically, specific circuits are developed
and integrated on-chip that can conduct tests when the chips are manufactured.
The data collected can be used to get statistical information about which parts of
the design that are most prone to failures.
In this thesis, a system has been implemented where fault-tolerant components
have been added to the interface between a 32-bit RISC-V core and its memory
subsystem. Because of the high memory usage, a memory built-in self-test has

been implemented and integrated to test and provide fault diagnosis. A built-
in self-test has also been developed to run diagnostic test of the fault-tolerant

components at the memory interfaces. The supply voltage was decreased lower
than the technology standard to decrease power usage. Voltage scaling provides
a trade-off between operational performance speed of the circuit and power. A
JTAG interface is used to control the system with configuration registers and to
perform memory operations such as inserting the program instruction that the
RISC-V core runs.

• author: Rodan, Mattias
• supervisor: Steffen Malkowsky
• organization: Department of Electrical and Information Technology
• course: EITM01 20201
• year: 2020
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: Testable, MBIST, Fault-tolerant, ECC, RISC-V
• report number: LU/LTH-EIT 2021-803
• language: English
• id: 9037414
• date added to LUP: 2021-02-04 10:21:51
• date last changed: 2021-02-04 10:21:51