Investigating Machine Learning for verification of AMBA APB protocol.

Abstract

It is a well-known fact that in any Application Specific Integrated Circuit (ASIC)
design, verification consumes most time and resources. And when it comes to huge
designs, finding bugs can be tedious given the area and the complexity. As per
Moore’s law, the design complexity is increasing exponentially due to the growing
demand for performance. Therefore, On-Chip communication becomes crucial.
The interconnects play a vital role in communication between two Intellectual
Properties (IP) in a System-on-Chip (SOC), which makes it an utmost priority
to verify the protocol. In order to achieve this, many test-scenarios are developed
which in turn increases the debug effort and verification space. As Advanced
Microcontroller Bus Architecture (AMBA) protocol is most commonly used as a
communication protocol, the Design Under Test (DUT) for this thesis is Advanced
Peripheral Bus (APB), a member of the AMBA family.
This thesis aims to investigate the applications of Machine Learning (ML) to
reduce the overall verification time and effort. Basic classifiers such as K-Nearest
Neighbors (KNN), Decision Trees (DT) are explored and studied, along with two
types of Neural Networks, such as the FeedForward Neural Network (FFNN) and
Recurrent Neural Network (RNN). These algorithms were trained overtime with
various datasets along with fine-tuning their respective parameters. The Long
Short Term Memory (LSTM) model, a variant of the RNN is the preferred among
other models as it is capable of learning the complete behavior of the APB. From
the results obtained, the LSTM was able to classify the write, read and the failed
transactions with an accuracy of 90%. The results also discusses the accuracy
obtained by other models and compares the time and effort taken to implement
all of them. The study is concluded with a belief that ML can be a method in
verification with suggested improvements. The ideas for future studies have been
briefly presented as well.

Popular Abstract

Having an implemented design and its specification on the same page is the crux
of any given ASIC. This desired overlapping is achieved by scrutinizing the design
at every stage of its design cycle. Verification of an ASIC has grown extensively
over the years from basic functional stimulus verification to formal verification
standards and etc., and this alone has resulted in various verification methodologies,
one such being Assertion Based Verification (ABV). Unlike earlier days,
verification engineers now have a huge demand in the industry. With growing design
complexities, it is important to verify the hardware with various tests before
tape-outs in order to avoid any possibility of a bug post tape-out.
Verifying large circuits comes with many challenges. Huge number of signals
spanning over millions of clock cycles and monitoring their behaviour is laborious
and time consuming. Although, assertions come in handy in highlighting the bugs,
writing assertions are not as simple as it looks. The complexity of the design is
directly proportional to the complexity of writing assertions.
On the other hand, with the advent of Machine Learning (ML), its extensive
usage in the development of newer technologies and simplifying existing practices
over the years has proven itself to be flexible and reliable. The ability to learn
features and either classify the nature or perform mathematical calculations and
predict the behavior in quantitative terms has paved a path for many industries,
engineers and students. Few of the examples where ML is dominating are Image
Processing, Robotics, Medical Engineering and Statistics. With various ML algorithms
ranging in their complexities and the nature of predictions, understanding
their behavior with regards to hardware design and verification can be helpful in
determining their competence and need for it. Presently, very few articles and
journals have been published as many leading industries such as Ericsson, ARM,
Cadence, Accellera, Xilinx are currently researching in this field.
Taking note of these challenges and approaches, the aim of this thesis is to
study and apply the concepts of machine learning in the field of hardware verification
to understand how it improvises the current state-of-the art methodologies.
A comparative study has been performed listing out its advantages and disadvantages
along with the results of various algorithms explored.

• author: Kishore, Abhiram Srisai and Wasim, Mohammed
• supervisor: Erik Larsson; Liang Liu
• organization: Department of Electrical and Information Technology
• course: EITM02 20201
• year: 2022
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: Machine learning, SOC Verification, AMBA, Neural Networks, Deep Learning, Assertions.
• report number: LU/LTH-EIT 2022-863
• language: English
• id: 9078450
• date added to LUP: 2022-04-25 15:01:54
• date last changed: 2022-04-25 15:01:54