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A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility

Kamuf, Matthias LU ; Öwall, Viktor LU ; Rodrigues, Joachim LU and Anderson, John B LU (2008) Norchip Conference, 2008 p.137-141
Abstract
This paper discusses design and measurements of

a flexible Viterbi decoder fabricated in 130-nm digital CMOS.

Flexibility was incorporated by providing various code rates and

modulation schemes to adjust to varying channel conditions.

Based on previous trade-off studies, flexible building blocks were

carefully designed to cause as little area penalty as possible. The

chip runs down to a minimal core supply of 0.8V. It turns out that

striving for more modulation schemes is beneficial in terms of

power consumption once the price is paid for accepting different

code rates viz. radices in the trellis and survivor path units.
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Viterbi decoder, CMOS, flexible chips, integrated circuits
host publication
Proceedings, Norchip Conference
pages
5 pages
conference name
Norchip Conference, 2008
conference location
Talinn, Estonia
conference dates
2008-11-16 - 2008-11-17
project
EIT_HSWC:Coding Coding, modulation, security and their implementation
language
English
LU publication?
yes
id
0e36834d-c97c-4936-88c9-b0486aca30f8 (old id 1259583)
date added to LUP
2016-04-04 14:28:48
date last changed
2018-11-21 21:20:34
@inproceedings{0e36834d-c97c-4936-88c9-b0486aca30f8,
  abstract     = {{This paper discusses design and measurements of<br/><br>
a flexible Viterbi decoder fabricated in 130-nm digital CMOS.<br/><br>
Flexibility was incorporated by providing various code rates and<br/><br>
modulation schemes to adjust to varying channel conditions.<br/><br>
Based on previous trade-off studies, flexible building blocks were<br/><br>
carefully designed to cause as little area penalty as possible. The<br/><br>
chip runs down to a minimal core supply of 0.8V. It turns out that<br/><br>
striving for more modulation schemes is beneficial in terms of<br/><br>
power consumption once the price is paid for accepting different<br/><br>
code rates viz. radices in the trellis and survivor path units.}},
  author       = {{Kamuf, Matthias and Öwall, Viktor and Rodrigues, Joachim and Anderson, John B}},
  booktitle    = {{Proceedings, Norchip Conference}},
  keywords     = {{Viterbi decoder; CMOS; flexible chips; integrated circuits}},
  language     = {{eng}},
  pages        = {{137--141}},
  title        = {{A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility}},
  url          = {{https://lup.lub.lu.se/search/files/6370021/1738162.pdf}},
  year         = {{2008}},
}