Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint
Larsson, Erik LU
and Edbom, Stina
(2007)
In IET Computers and Digital Techniques
1(1).
p.27-37
- Abstract
- Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect... (More)
- Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2341028
- author
- Larsson, Erik
LU
and Edbom, Stina
- publishing date
- 2007
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- testing, electronic systems, memory constraints
- in
- IET Computers and Digital Techniques
- volume
- 1
- issue
- 1
- pages
- 27 - 37
- publisher
- John Wiley & Sons Inc.
- ISSN
- 1751-8601
- DOI
- 10.1049/iet-cdt:20050209
- language
- English
- LU publication?
- no
- id
- 9633dbc8-3eb9-4e60-b5bd-1ce80205aec9 (old id 2341028)
- alternative location
- http://www.ida.liu.se/labs/eslab/publications/pap/db/erila_iet07.pdf
- date added to LUP
- 2016-04-04 07:07:19
- date last changed
- 2025-04-04 13:53:39
@article{9633dbc8-3eb9-4e60-b5bd-1ce80205aec9,
abstract = {{Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.}},
author = {{Larsson, Erik and Edbom, Stina}},
issn = {{1751-8601}},
keywords = {{testing; electronic systems; memory constraints}},
language = {{eng}},
number = {{1}},
pages = {{27--37}},
publisher = {{John Wiley & Sons Inc.}},
series = {{IET Computers and Digital Techniques}},
title = {{Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint}},
url = {{http://dx.doi.org/10.1049/iet-cdt:20050209}},
doi = {{10.1049/iet-cdt:20050209}},
volume = {{1}},
year = {{2007}},
}