A Highly Parallelized MIMO Detector for Vector-Based Reconfigurable Architectures
(2013) IEEE Wireless Communications and Networking Conference (WCNC), 2013 p.3844-3849- Abstract
- This paper presents a highly parallelized MIMO signal detection algorithm targeting vector-based reconfigurable architectures. The detector achieves high data-level parallelism and near-ML performance by adopting a vector-architecture-friendly technique - parallel node perturbation. To further reduce the computational complexity, imbalanced node and successive partial node expansion schemes in conjunction with sorted QR decomposition are applied. The effectiveness of the proposed algorithm is evaluated by simulations performed on a simplified 4x4 MIMO LTE-A testbed and operation analysis. Compared to the K-Best detector and fixed-complexity sphere decoder (FSD), the number of visited nodes in the proposed algorithm is reduced by 15 and 1.9... (More)
- This paper presents a highly parallelized MIMO signal detection algorithm targeting vector-based reconfigurable architectures. The detector achieves high data-level parallelism and near-ML performance by adopting a vector-architecture-friendly technique - parallel node perturbation. To further reduce the computational complexity, imbalanced node and successive partial node expansion schemes in conjunction with sorted QR decomposition are applied. The effectiveness of the proposed algorithm is evaluated by simulations performed on a simplified 4x4 MIMO LTE-A testbed and operation analysis. Compared to the K-Best detector and fixed-complexity sphere decoder (FSD), the number of visited nodes in the proposed algorithm is reduced by 15 and 1.9 times respectively, with less than 1dB performance degradation. Benefiting from the fully deterministic non-iterative dataflow structure, reconfiguration rate is 95% less than that of the K-Best detector and 17% less than the case of FSD. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3438121
- author
- Zhang, Chenxin
LU
; Liu, Liang
LU
; Wang, Yian ; Zhu, Meifang LU ; Edfors, Ove LU
and Öwall, Viktor LU
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- MIMO, signal detection, vector processor, data parallelization
- host publication
- [Host publication title missing]
- pages
- 6 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE Wireless Communications and Networking Conference (WCNC), 2013
- conference location
- Shanghai, China
- conference dates
- 2013-04-07 - 2013-04-10
- external identifiers
-
- wos:000326048103162
- scopus:84881591038
- DOI
- 10.1109/WCNC.2013.6555188
- project
- High Performance Embedded Computing
- EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
- language
- English
- LU publication?
- yes
- id
- 5ec50c19-8da4-48d2-bb62-a716ee62ef5a (old id 3438121)
- alternative location
- http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6555188&tag=1
- date added to LUP
- 2016-04-04 10:16:06
- date last changed
- 2024-01-12 19:31:53
@inproceedings{5ec50c19-8da4-48d2-bb62-a716ee62ef5a, abstract = {{This paper presents a highly parallelized MIMO signal detection algorithm targeting vector-based reconfigurable architectures. The detector achieves high data-level parallelism and near-ML performance by adopting a vector-architecture-friendly technique - parallel node perturbation. To further reduce the computational complexity, imbalanced node and successive partial node expansion schemes in conjunction with sorted QR decomposition are applied. The effectiveness of the proposed algorithm is evaluated by simulations performed on a simplified 4x4 MIMO LTE-A testbed and operation analysis. Compared to the K-Best detector and fixed-complexity sphere decoder (FSD), the number of visited nodes in the proposed algorithm is reduced by 15 and 1.9 times respectively, with less than 1dB performance degradation. Benefiting from the fully deterministic non-iterative dataflow structure, reconfiguration rate is 95% less than that of the K-Best detector and 17% less than the case of FSD.}}, author = {{Zhang, Chenxin and Liu, Liang and Wang, Yian and Zhu, Meifang and Edfors, Ove and Öwall, Viktor}}, booktitle = {{[Host publication title missing]}}, keywords = {{MIMO; signal detection; vector processor; data parallelization}}, language = {{eng}}, pages = {{3844--3849}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A Highly Parallelized MIMO Detector for Vector-Based Reconfigurable Architectures}}, url = {{https://lup.lub.lu.se/search/files/5500673/5385567.pdf}}, doi = {{10.1109/WCNC.2013.6555188}}, year = {{2013}}, }