Development and Implementation of Cardiac Event Detectors in Digital CMOS

Abstract

This doctoral dissertation presents the development and digital hardware realization of cardiac event detectors. Implantable medical



appliances, as the cardiac pacemaker, have progressed from a life



sustaining device to a device that considerably improves life



quality for all ages. The number of electronic devices and household



appliances in everyday live has an ongoing exponential growth. These



devices contaminate their environment with electronic, magnetic or



electromagnetic radiation. Pacemaker patients exposed to this



environment may suffer due to malfunction of the pacemaker. Thus,



the next generation of pacemakers require a low-power consuming



event detector that provides reliable detection performance.



In this thesis two papers that present an artificial neural network



based event detector for R-wave detection are merged to an extended



manuscript. The neural network functions as a whitening filter prior



to a matched filter. It is shown how the neural network responds to



sudden changes in the input sequence. An algorithm that determines



the initial template for matched filtering is proposed, and a



continuous update of the filter impulse response is implemented in



order to track long-term changes in signal morphology. Furthermore,



an updated threshold function is proposed which addresses amplitude



variations in the electrogram. Noise suppression and classification



performance under ``real-life situation'' are explored by analyzing



recordings from databases of electrograms and noise. Finally, the



suitability for pacemaker application is discussed.



Four papers that present a low-power digital hardware implementation



of a wavelet based event detector are merged and extended in the



second part of this thesis. The theory of the wavelet filterbank is



presented, and it is shown how the architecture was modified to



achieve an area and power efficient silicon implementation. An



algorithm is presented that determines automatically a threshold



level during the initialization phase. A second operation mode is



proposed to shut down major parts of the hardware, if the patient is



at rest or in a ``low-noise'' environment. Power analysis on



RTL-level shows that leakage power is the dominant factor in the



total power figure. An estimate for leakage reduction is presented



if sleep transistors are introduced between the supply rails and the



logic that is shut-off in low-noise operation mode. The R-wave



detector has been implemented in 0.13$,mu$m low-leakage CMOS



technology. The design has been routed, and, thereafter, sleep



transistors are introduced in the layout. Detection performance is



evaluated by means of databases containing electrograms to which



five types of exogenic and endogenic interference are added. The



results show that reliable detection is obtained at moderate and low



SNRs.

• author: Rodrigues, Joachim
• supervisor: Viktor Öwall
• opponent: Professor Lande, Tor Sverre, Dept. of Informatics, University of Oslo
• organization: Department of Electrical and Information Technology
• publishing date: 2005
• type: Thesis
• publication status: published
• subject: Electrical Engineering, Electronic Engineering, Information Engineering
• keywords: Signal processing, Elektronik och elektroteknik, Electronics and Electrical technology, event detection, cardiac pacemaker, sleep- transistors, low-power, ASIC, Neural Networks, Electrogram, Signalbehandling, Wavelets
• pages: 174 pages
• defense location: Room E:1406, E-building, Ole Römers väg 3, Lund Institute of Technology
• defense date: 2005-10-07 10:15:00
• ISBN: 1402866256
• language: Swedish
• LU publication?: yes
• id: da485c66-43f0-48c8-96fe-b0bcce24573b (old id 545396)
• date added to LUP: 2016-04-04 10:00:54
• date last changed: 2018-11-21 20:56:13