Self-similar module for FP/LNS arithmetic in high-performance FPGA systems
(2005) VLSI Circuits and Systems II 5837 PART II. p.880-887- Abstract
- The scientific community has gratefully embraced floating-point arithmetic to escape the close attention for accuracy and precision required in fixed-point computational styles. Though its deficiencies are well known, the role of the floating-point system as standard has kept other number representation systems from coming into practice. The paper discusses the relation between fixed and floating-point numbers from a pragmatic point of view that allows to mix both systems to optimize FPGA-based hardware accelerators. The method is developed for the Mitrion "processor on demand" technology, where a computationally intensive algorithm is transformed into a dedicated. The large gap in cycle time between fixed and floating-point operations and... (More)
- The scientific community has gratefully embraced floating-point arithmetic to escape the close attention for accuracy and precision required in fixed-point computational styles. Though its deficiencies are well known, the role of the floating-point system as standard has kept other number representation systems from coming into practice. The paper discusses the relation between fixed and floating-point numbers from a pragmatic point of view that allows to mix both systems to optimize FPGA-based hardware accelerators. The method is developed for the Mitrion "processor on demand" technology, where a computationally intensive algorithm is transformed into a dedicated. The large gap in cycle time between fixed and floating-point operations and between direct and reverse operations makes the on-chip control for the fine-grain pipelines of parallel logic very complicated. Having alternative hardware realizations available can alleviate this. The paper uses a conjunctive notation, also known as DIGILOG, to introduce a flexible means in creating configurable arithmetic of arbitrary order using a single module type. This allows the Mitrion hardware compiler to match the hardware closer to the demands of the specific algorithm. Typical applications are in molecular simulation and real-time image analysis. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/615731
- author
- Spaanenburg, Lambert LU and Mohl, Stefan
- organization
- publishing date
- 2005
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- Floating-point number system, Computer arithmetic, Mixed logarithmic number system, Network on a chip
- host publication
- Proceedings of SPIE - The International Society for Optical Engineering
- volume
- 5837 PART II
- pages
- 880 - 887
- publisher
- International Society for Optical Engineering
- conference name
- VLSI Circuits and Systems II
- conference location
- Seville, Spain
- conference dates
- 2005-05-09 - 2005-05-11
- external identifiers
-
- wos:000231723000089
- scopus:28344444119
- ISSN
- 1996-756X
- 0277-786X
- DOI
- 10.1117/12.608537
- language
- English
- LU publication?
- yes
- id
- 5100b0af-24ef-4938-a79b-5a40878d72df (old id 615731)
- date added to LUP
- 2016-04-01 11:56:13
- date last changed
- 2024-01-08 02:03:09
@inproceedings{5100b0af-24ef-4938-a79b-5a40878d72df, abstract = {{The scientific community has gratefully embraced floating-point arithmetic to escape the close attention for accuracy and precision required in fixed-point computational styles. Though its deficiencies are well known, the role of the floating-point system as standard has kept other number representation systems from coming into practice. The paper discusses the relation between fixed and floating-point numbers from a pragmatic point of view that allows to mix both systems to optimize FPGA-based hardware accelerators. The method is developed for the Mitrion "processor on demand" technology, where a computationally intensive algorithm is transformed into a dedicated. The large gap in cycle time between fixed and floating-point operations and between direct and reverse operations makes the on-chip control for the fine-grain pipelines of parallel logic very complicated. Having alternative hardware realizations available can alleviate this. The paper uses a conjunctive notation, also known as DIGILOG, to introduce a flexible means in creating configurable arithmetic of arbitrary order using a single module type. This allows the Mitrion hardware compiler to match the hardware closer to the demands of the specific algorithm. Typical applications are in molecular simulation and real-time image analysis.}}, author = {{Spaanenburg, Lambert and Mohl, Stefan}}, booktitle = {{Proceedings of SPIE - The International Society for Optical Engineering}}, issn = {{1996-756X}}, keywords = {{Floating-point number system; Computer arithmetic; Mixed logarithmic number system; Network on a chip}}, language = {{eng}}, pages = {{880--887}}, publisher = {{International Society for Optical Engineering}}, title = {{Self-similar module for FP/LNS arithmetic in high-performance FPGA systems}}, url = {{http://dx.doi.org/10.1117/12.608537}}, doi = {{10.1117/12.608537}}, volume = {{5837 PART II}}, year = {{2005}}, }