ISO/OSI compliant network-on-chip implementation for CNN applications
(2005) Bioengineered and Bioinspired Systems II 5839(1). p.341-352- Abstract
- The paper investigates the potential for a packet switching network for real-time image processing by a Cellular Neural Network (CNN) implemented on a Field-Programmable Gate-Array (FPGA). The implementation of a CNN requires several parameter restrictions with respect to the universal concept. For instance, the number representation and the cloning template are often confined to respectively 8 bits and a neighborhood of 1. It has been shown that optimal (i.e. minimal level) CNN architectures as derived from a morphological specification of the desired operation lead to arbitrarily large templates. A subsequent transformation step can turn this into a sequence of smaller templates for a specified hardware platform. The existence of a... (More)
- The paper investigates the potential for a packet switching network for real-time image processing by a Cellular Neural Network (CNN) implemented on a Field-Programmable Gate-Array (FPGA). The implementation of a CNN requires several parameter restrictions with respect to the universal concept. For instance, the number representation and the cloning template are often confined to respectively 8 bits and a neighborhood of 1. It has been shown that optimal (i.e. minimal level) CNN architectures as derived from a morphological specification of the desired operation lead to arbitrarily large templates. A subsequent transformation step can turn this into a sequence of smaller templates for a specified hardware platform. The existence of a generic platform that can already handle the universal CNN architecture for prototyping and verification eliminates this need for technology-driven performance degradation. The proposed packet switcher consists of a physical layer where the CNN nodal function is performed, a data-link layer where the nodal data are maintained, a network layer with the packet receiver and sender and the actual switch as element of the transport layer. This ISO/OSI compliant level-wise structure monitors the network parameters and autonomously adjusts for the size of the neighborhood. It separates the broadcast of the network variables from the actual computation, allowing each to be executed at its own speed. The concept is tested on a re-design of the ILVA architecture and has been shown to handle arbitrary neighborhoods and precision at a comparable size and speed (1 node per BlockRAM / multiplier module @220 MHz clock) (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/616566
- author
- Malki, Suleyman LU ; Hansson, A ; Spaanenburg, Lambert LU and Akesson, B
- organization
- publishing date
- 2005
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- technology-driven performance degradation, field-programmable gate-array, cellular neural network, real-time image processing, network-on-chip implementation, packet switching network
- host publication
- Proceedings of the SPIE - The International Society for Optical Engineering
- volume
- 5839
- issue
- 1
- pages
- 341 - 352
- publisher
- SPIE
- conference name
- Bioengineered and Bioinspired Systems II
- conference location
- Sevilla, Spain
- conference dates
- 2005-05-09
- external identifiers
-
- wos:000231788300035
- scopus:28344437826
- ISSN
- 0277-786X
- 1996-756X
- DOI
- 10.1117/12.608534
- language
- English
- LU publication?
- yes
- id
- cf83becf-2fa7-4be5-9d74-dcca87a36091 (old id 616566)
- date added to LUP
- 2016-04-01 11:52:10
- date last changed
- 2024-01-07 23:35:55
@inproceedings{cf83becf-2fa7-4be5-9d74-dcca87a36091,
abstract = {{The paper investigates the potential for a packet switching network for real-time image processing by a Cellular Neural Network (CNN) implemented on a Field-Programmable Gate-Array (FPGA). The implementation of a CNN requires several parameter restrictions with respect to the universal concept. For instance, the number representation and the cloning template are often confined to respectively 8 bits and a neighborhood of 1. It has been shown that optimal (i.e. minimal level) CNN architectures as derived from a morphological specification of the desired operation lead to arbitrarily large templates. A subsequent transformation step can turn this into a sequence of smaller templates for a specified hardware platform. The existence of a generic platform that can already handle the universal CNN architecture for prototyping and verification eliminates this need for technology-driven performance degradation. The proposed packet switcher consists of a physical layer where the CNN nodal function is performed, a data-link layer where the nodal data are maintained, a network layer with the packet receiver and sender and the actual switch as element of the transport layer. This ISO/OSI compliant level-wise structure monitors the network parameters and autonomously adjusts for the size of the neighborhood. It separates the broadcast of the network variables from the actual computation, allowing each to be executed at its own speed. The concept is tested on a re-design of the ILVA architecture and has been shown to handle arbitrary neighborhoods and precision at a comparable size and speed (1 node per BlockRAM / multiplier module @220 MHz clock)}},
author = {{Malki, Suleyman and Hansson, A and Spaanenburg, Lambert and Akesson, B}},
booktitle = {{Proceedings of the SPIE - The International Society for Optical Engineering}},
issn = {{0277-786X}},
keywords = {{technology-driven performance degradation; field-programmable gate-array; cellular neural network; real-time image processing; network-on-chip implementation; packet switching network}},
language = {{eng}},
number = {{1}},
pages = {{341--352}},
publisher = {{SPIE}},
title = {{ISO/OSI compliant network-on-chip implementation for CNN applications}},
url = {{http://dx.doi.org/10.1117/12.608534}},
doi = {{10.1117/12.608534}},
volume = {{5839}},
year = {{2005}},
}