A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS
Abdulaziz, Mohammed LU ; Forsberg, Therese LU ; Törmänen, Markus LU
and Sjöland, Henrik
LU
(2019)
In IEEE Transactions on Microwave Theory and Techniques
67(4).
p.1588-1600
- Abstract
- This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator... (More)
- This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator CMOS process, and its active area is just 0.19 mm². The PLL also features a novel double injection-locked divide-by-3 circuit and a charge-pump mismatch compensation scheme, resulting in state-of-the-art power consumption, and jitter performance in the low-noise mode. In this mode, the in-band phase noise is between -93 and -96 dBc/Hz across the tuning range, and the integrated jitter is between 176 and 212 fs. The total power consumption of the mm-wave PLL is only 10.1 mW, resulting in a best-case PLL figure-of-merit (FOM) of -245 dB. The lock time in low-noise mode is up to 12 μs, which is improved to 3 μs by switching to the fast-locking mode, at the temporary expense of a power consumption increase to 15.1 mW, an integrated jitter increase to between 245 and 433 fs, and an FOM increase to between -235 and -240 dB. (Less)
- Abstract (Swedish)
- This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency
alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator... (More) - This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency
alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator CMOS process, and its active area is just 0.19 mm2. The PLL also features a novel double injection-locked divide-by-3 circuit and a charge-pump mismatch compensation
scheme, resulting in state-of-the-art power consumption, and jitter performance in the low-noise mode. In this mode, the inband phase noise is between −93 and −96 dBc/Hz across the tuning range, and the integrated jitter is between 176 and 212 fs. The total power consumption of the mm-wave PLL is only 10.1 mW, resulting in a best-case PLL figure-of-merit (FOM) of −245 dB. The lock time in low-noise mode is up to 12 μs, which is improved to 3 μs by switching to the fast-locking mode, at the temporary expense of a power consumption increase to 15.1 mW, an integrated jitter increase to between 245 and 433 fs, and an FOM increase to between −235 and −240 dB. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/a34bdcc4-ffe1-4e78-8fbc-2f691f54e228
- author
- Abdulaziz, Mohammed
LU
; Forsberg, Therese
LU
; Törmänen, Markus
LU
and Sjöland, Henrik
LU
- organization
- publishing date
- 2019
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Charge pump, CMOS, Divide-by-3, Fast lock time, 5G, Frequency synthesizers, Injection-locked divider, ILFD, Local oscillator, Low phase noise, Low power, phase-locked loop (PLL), 60 GHz
- in
- IEEE Transactions on Microwave Theory and Techniques
- volume
- 67
- issue
- 4
- pages
- 13 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:85064067327
- ISSN
- 0018-9480
- DOI
- 10.1109/TMTT.2019.2896566
- project
- Efficient mm-Wave Transmitter Design in CMOS Technology
- language
- English
- LU publication?
- yes
- id
- a34bdcc4-ffe1-4e78-8fbc-2f691f54e228
- date added to LUP
- 2019-02-24 01:06:50
- date last changed
- 2024-02-14 18:22:52
@article{a34bdcc4-ffe1-4e78-8fbc-2f691f54e228,
abstract = {{This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator CMOS process, and its active area is just 0.19 mm². The PLL also features a novel double injection-locked divide-by-3 circuit and a charge-pump mismatch compensation scheme, resulting in state-of-the-art power consumption, and jitter performance in the low-noise mode. In this mode, the in-band phase noise is between -93 and -96 dBc/Hz across the tuning range, and the integrated jitter is between 176 and 212 fs. The total power consumption of the mm-wave PLL is only 10.1 mW, resulting in a best-case PLL figure-of-merit (FOM) of -245 dB. The lock time in low-noise mode is up to 12 μs, which is improved to 3 μs by switching to the fast-locking mode, at the temporary expense of a power consumption increase to 15.1 mW, an integrated jitter increase to between 245 and 433 fs, and an FOM increase to between -235 and -240 dB.}},
author = {{Abdulaziz, Mohammed and Forsberg, Therese and Törmänen, Markus and Sjöland, Henrik}},
issn = {{0018-9480}},
keywords = {{Charge pump; CMOS; Divide-by-3; Fast lock time; 5G; Frequency synthesizers; Injection-locked divider; ILFD; Local oscillator; Low phase noise; Low power; phase-locked loop (PLL); 60 GHz}},
language = {{eng}},
number = {{4}},
pages = {{1588--1600}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
series = {{IEEE Transactions on Microwave Theory and Techniques}},
title = {{A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS}},
url = {{http://dx.doi.org/10.1109/TMTT.2019.2896566}},
doi = {{10.1109/TMTT.2019.2896566}},
volume = {{67}},
year = {{2019}},
}