Ping Lu (Former)
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- 2011
-
Mark
A Digital PLL with a Multi-Delay Coarse-Fine TDC
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 0.13µm CMOS ΔΣ PLL FM Transmitter
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS
2010) NORCHIP Conference, 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2009
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to conference › Paper, not in proceeding
-
Mark
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2008
-
Mark
A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM
2008) Norchip Conference, 2008(
- Contribution to conference › Paper, not in proceeding
- 2007
-
Mark
A 4 GHz ring oscillator based on dual-feedback loops with PVT deviation adaption
(
- Contribution to journal › Article
-
Mark
A low-jitter clock generator for HDTV
(
- Contribution to journal › Article
- 2006
-
Mark
A low-jitter and low-power frequency synthesizer applied to 1000 Base-T Ethernet
(
- Contribution to journal › Article