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A Digital PLL with a Multi-Delay Coarse-Fine TDC

Wu, Ying ; Lu, Ping LU and Andreani, Pietro LU (2011) 29th Norchip conference, 2011
Abstract
A 5GHz digital frequency synthesizer achieving a low noise for wireless RF application is presented. This architecture uses a multi-delay coarse-fine Time-to-Digital Converter (TDC) to achieve both the large detection range and fine resolution. A Digitally Controlled Oscillator (DCO) based on capacitive degeneration in LC-Tank is also implement-ed. The DCO achieves frequency quantization step of 300 Hz without any dithering. Simulated phase noise at 5 GHz carrier frequency is -125 and -151 dBc/Hz at 1 MHz and 20 MHz offset, respectively. The Digital phase-locked loop (DPLL) is realized in 90nm CMOS process and consumes 14mA from a 1.2V supply.
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
[Host publication title missing]
pages
4 pages
conference name
29th Norchip conference, 2011
conference location
Lund, Sweden
conference dates
2011-11-14 - 2011-11-15
external identifiers
  • scopus:84863038791
ISBN
978-1-4577-0514-4
DOI
10.1109/NORCHP.2011.6126745
language
English
LU publication?
yes
id
af9f62c3-30f5-472d-888c-61a4c071c9b4 (old id 2437170)
date added to LUP
2016-04-04 12:53:03
date last changed
2022-01-29 23:30:23
@inproceedings{af9f62c3-30f5-472d-888c-61a4c071c9b4,
  abstract     = {{A 5GHz digital frequency synthesizer achieving a low noise for wireless RF application is presented. This architecture uses a multi-delay coarse-fine Time-to-Digital Converter (TDC) to achieve both the large detection range and fine resolution. A Digitally Controlled Oscillator (DCO) based on capacitive degeneration in LC-Tank is also implement-ed. The DCO achieves frequency quantization step of 300 Hz without any dithering. Simulated phase noise at 5 GHz carrier frequency is -125 and -151 dBc/Hz at 1 MHz and 20 MHz offset, respectively. The Digital phase-locked loop (DPLL) is realized in 90nm CMOS process and consumes 14mA from a 1.2V supply.}},
  author       = {{Wu, Ying and Lu, Ping and Andreani, Pietro}},
  booktitle    = {{[Host publication title missing]}},
  isbn         = {{978-1-4577-0514-4}},
  language     = {{eng}},
  title        = {{A Digital PLL with a Multi-Delay Coarse-Fine TDC}},
  url          = {{http://dx.doi.org/10.1109/NORCHP.2011.6126745}},
  doi          = {{10.1109/NORCHP.2011.6126745}},
  year         = {{2011}},
}