Matthias Kamuf
1 – 10 of 16
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=""
width=""
height=""
allowtransparency="true"
frameborder="0">
</iframe>
- 2010
- Modification of SOVA-based Algorithms for Efficient Hardware Implementation
- 2008
- Reducing computational complexity of branch metric calculations in a trellis decoder
- A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
- 2007
- Trellis Decoding: From Algorithm to Flexible Architectures
- Survivor path processing in Viterbi decoders using register exchange and traceforward
- 2006
- Architectural Optimization for Low power in a Reconfigurable UMTS filter
- 2005
- A hardware efficiency analysis for simplified trellis decoding blocks
- Teaching digital ASIC design to students with heterogeneoms previous knowledge
- Architectural considerations for rate-flexible trellis processing blocks
- Area and power efficient trellis computational blocks in 0.13μm CMOS