Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping
(2011) IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011 p.1696-1699- Abstract
- This paper presents a flexible architecture suitable for concurrent processing of multiple radio standards. The proposed architecture is based on a coarse-grained reconfigurable cell array, consisting of distinct processing and memory cells. Flexibility of the architecture is demonstrated by performing a coarse time synchronization and fractional frequency offset estimation for multiple OFDM standards. The radio standards under analysis are IEEE 802.11n, LTE, and DVB-H. The reconfigurable cell array, containing 2-by-2 cells, is capable of processing two concurrent data streams from the standards. Dynamic reconfigurability of the architecture enables run-time switching between the standards. The implemented 2-by-2 cell array is synthesized... (More)
- This paper presents a flexible architecture suitable for concurrent processing of multiple radio standards. The proposed architecture is based on a coarse-grained reconfigurable cell array, consisting of distinct processing and memory cells. Flexibility of the architecture is demonstrated by performing a coarse time synchronization and fractional frequency offset estimation for multiple OFDM standards. The radio standards under analysis are IEEE 802.11n, LTE, and DVB-H. The reconfigurable cell array, containing 2-by-2 cells, is capable of processing two concurrent data streams from the standards. Dynamic reconfigurability of the architecture enables run-time switching between the standards. The implemented 2-by-2 cell array is synthesized using a 65 nm low-leakage standard cell CMOS library, resulting in an area of 0.479mm2 and a maximum clock frequency of 534MHz. High flexibility offered by the reconfigurable cell array allows the adoption of different algorithms onto the same platform. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2429882
- author
- Zhang, Chenxin LU ; Diaz, Isael LU ; Andersson, Per LU ; Rodrigues, Joachim LU and Öwall, Viktor LU
- organization
- publishing date
- 2011
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- CGRA, Reconfigurable cell array, Multi-standard, Concurrent, OFDM, Synchronization
- host publication
- IEEE International Symposium on Circuits and Systems
- pages
- 1696 - 1699
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011
- conference location
- Rio de Janeiro, Brazil
- conference dates
- 2011-05-15 - 2011-05-18
- external identifiers
-
- wos:000297265302005
- scopus:79960886502
- ISSN
- 2158-1525
- 0271-4310
- ISBN
- 978-1-4244-9473-6
- DOI
- 10.1109/ISCAS.2011.5937908
- project
- EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
- language
- English
- LU publication?
- yes
- additional info
- Best Student Paper award at ISCAS 2014.
- id
- 016ea851-9aa2-42c2-b26e-90089ce77429 (old id 2429882)
- date added to LUP
- 2016-04-01 10:27:57
- date last changed
- 2025-01-14 15:32:57
@inproceedings{016ea851-9aa2-42c2-b26e-90089ce77429, abstract = {{This paper presents a flexible architecture suitable for concurrent processing of multiple radio standards. The proposed architecture is based on a coarse-grained reconfigurable cell array, consisting of distinct processing and memory cells. Flexibility of the architecture is demonstrated by performing a coarse time synchronization and fractional frequency offset estimation for multiple OFDM standards. The radio standards under analysis are IEEE 802.11n, LTE, and DVB-H. The reconfigurable cell array, containing 2-by-2 cells, is capable of processing two concurrent data streams from the standards. Dynamic reconfigurability of the architecture enables run-time switching between the standards. The implemented 2-by-2 cell array is synthesized using a 65 nm low-leakage standard cell CMOS library, resulting in an area of 0.479mm2 and a maximum clock frequency of 534MHz. High flexibility offered by the reconfigurable cell array allows the adoption of different algorithms onto the same platform.}}, author = {{Zhang, Chenxin and Diaz, Isael and Andersson, Per and Rodrigues, Joachim and Öwall, Viktor}}, booktitle = {{IEEE International Symposium on Circuits and Systems}}, isbn = {{978-1-4244-9473-6}}, issn = {{2158-1525}}, keywords = {{CGRA; Reconfigurable cell array; Multi-standard; Concurrent; OFDM; Synchronization}}, language = {{eng}}, pages = {{1696--1699}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping}}, url = {{http://dx.doi.org/10.1109/ISCAS.2011.5937908}}, doi = {{10.1109/ISCAS.2011.5937908}}, year = {{2011}}, }